Keeping current feedback amplifiers stable

Article By : Thomas Kugelstadt

This article provides design tips on how to ensure amplifier stability without delving into the mathematics of the underlying principles.

Current feedback (CFB) amplifiers can exhibit high gain peaking and become unstable, and for various reasons even turn into oscillators. The two major causes for amplifier instability are making the value of the feedback resistor too low, and introducing parasitic input and output capacitances with regard to ground. While small capacitances cause the amplifier’s frequency response to peak at high frequencies, high capacitance values can force the device into self-sustaining oscillations, where it ignores any input signal stimuli.

This article provides design tips on how to ensure amplifier stability. Following the dos and don’ts enables the reader to design stable amplifier circuits without delving into the mathematics of the underlying principles.

There are three main ways to minimize the effects of parasitic capacitances on the amplifier’s stability:

  1. Good layout techniques to minimize parasitic board and probe capacitances
  2. Use the CFB amplifier manufacturer’s specified feedback and gain resistor values, as these provide sufficient phase margin to tolerate small parasitic capacitances
  3. Use compensation techniques that minimize peaking of the frequency response and overshoots in the pulse response

Board layout tips
Achieving optimum performance with CFB amplifiers requires careful attention to board layout parasitics as well as external component types and resistor values. Referring to Figures 1 and 2, the following recommendations help optimize circuit performance:

  • Buffer the power supply pins with decoupling capacitors for low and high frequencies. For high frequencies use 100nF and 100pF capacitors in parallel and place them less than ¼ inch (6mm) from the supply pin. For low frequencies, use 6.8μF tantalum capacitors, which can be placed farther away from the amplifier, and allows them to be shared among other devices. Avoid narrow power and ground traces to minimize trace inductance, particularly between the power supply pins and the decoupling capacitors.
  • Because the amplifier’s output and inverting input pins are the most sensitive to parasitic capacitance, connect the output resistor, RS (if required) close to the output pin, and the feedback and gain resistor (RF and RG) close to the inverting input. These resistors isolate their respective pins from any trace capacitance.
  • Design placeholders for RIN and CIN at the non-inverting input. These might be required to compensate the gain peak caused by the parasitic capacitance (CPI) at the inverting input.
  • Determine whether an output isolation resistor is needed. Low parasitic capacitive loads (< 5pF) often do not need an RS. Also, higher parasitic output capacitances can be driven without RS, but will require a higher closed-loop gain setting.
  • Maintain ground and power plane-free areas around the input and output pins to minimize the build-up of AC-ground related capacitances. Elsewhere on the board, the ground- and power-planes should remain unbroken.
  • Connect each test point through a 100Ω resistor to the trace to be measured. This resistor isolates the probe capacitance oscilloscope from the signal trace.
Figure 1 CFB amplifier with parasitic capacitances and compensation components, RS, RIN, and CIN
Figure 2 Suggested layout for 2-layer PCB with ground-free window using the specified RF values

Manufacturers of CFB amplifiers commonly specify multiple RF values, each corresponding to a different gain setting. Applying the recommended resistor values ensures optimum performance without (or only little) gain peaking or bandwidth reduction. Deviating from these values modifies amplifier performance. Figure 3 depicts this by using different RF values for a signal gain of two. The optimized and specified value of RF = 1.1kΩ for this gain shows optimal performance. However, when raising RF to 1.5kΩ, a reduction in bandwidth occurs, and when lowering RF to 600Ω, gain peaking occurs (Figure 4).

Therefore, to achieve optimum performance, follow the manufacturer’s recommended RF values.

Figure 3 Using RF values specified in the data sheet ensures best performance.

Figure 4 Deviating from the specified RF values causes gain peaking or reduced bandwidth

Compensating the effects of parasitic capacitance
To distinguish between the parasitic capacitance at the input (CPI) and the output (CPO), the pulse-response test can be applied. CPI, which is usually smaller than CPO, causes short signal overshoots, while CPO often results in prolonged signal ringing (Figure 5). Of course, the situation is reversed if CPI > CPO. This however, is rarely the case.

Figure 5 Signal overshoots due to CPI versus signal ringing due to CPO

[Continue reading on EDN US: Parasitic input capacitance]

Tom Kugelstadt is a principal applications engineer with Renesas Electronics America where he defines new high-performance analog products for industrial systems.

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