LED boost devices improve display efficiency

Article By : Jason Ngai

New LED boost devices lower form factor, operating temperature, and EMI for LCD panels serving mobile computing applications.

The LED backlight in an LCD panel is the biggest power hog in notebook and tablet applications. As screen resolution and brightness level increase, the input power consumed by the LED backlight increases as well. The existing conventional LED drivers on the market are reaching the peak performance and hitting the ceiling without any further gain in efficiency.

So, a new type of LED boost driver architecture is needed for a significant efficiency performance breakthrough to enable low power LCD panels for next-generation notebook and tablet designs. This article discusses a new LED boost architecture and outlines its advantage over conventional LED boost drivers.

Conventional LED boost architecture

Today’s conventional LED boost drivers use a single-stage asynchronous boost DC-DC architecture. This DC-DC architecture is used because of the high-output voltage required by the LED strings. Because of this high-output voltage, it makes less economic sense to integrate a high-voltage, large-size P-channel MOSFET for a synchronous converter in the LED boost driver.

Additionally, the forward voltage drop in a Schottky diode in an asynchronous converter impacts the efficiency by only 0.5 to 1%. For these two reasons, an asynchronous boost architecture is the preferred approach for today’s LED boost drivers. A simplified circuit for the conventional LED boost driver is shown in Figure 1.

circuit diagram of a conventional LED boost driverFigure 1 A simplified circuit diagram shows the conventional LED boost architecture. Source: pSemi

Conventional LED boost architecture is simple-to-use circuit but has several disadvantages. Efficiency is reduced as output voltage (VOUT) increases due to the increase in the conversion ratio. This forces many applications to use fewer series LEDs to reduce output voltage but also increases the number of parallel LED strings. More parallel LED strings require a wider bezel to accommodate more routing. This conventional architecture also reduces system efficiency due to more losses in LED current sinks’ regulation voltage (VREG). For a typical VREG of 0.4V and VOUT of 24V, the VREG contributes to a 1.67% system efficiency loss (VREG loss = VREG/VOUT*100%). Figure 2 shows the efficiency impact at two different VOUT levels.

graph of VOUT efficiencyFigure 2 Notice the ~2% efficiency drop as VOUT increases from 26 to 34V at the 5-W output power level. Source: pSemi

In conventional architecture, a larger inductor must be used to maintain high efficiency. This architecture occupies more board space and increases cost, making a low-profile design more challenging.

The asynchronous architecture creates a path between VIN and GND if VOUT is shorted to GND, enhancing the potential for catastrophic failure. Preventive solutions include either placing an input disconnect FET such as Q1 in Figure 1 or placing a fuse in the VIN path. This solution requires additional board space and increases the material cost and system efficiency loss.

Two-stage LED boost architecture

The unique LED boost explained in this article uses a two-stage DC-DC architecture. The first stage is a synchronous, inductive-based boost DC-DC converter. The second stage is a proprietary, capacitive-based charge pump circuit. This charge pump circuit provides a fixed 2x or 3x conversion from the boost output (VX) to the LED VOUT with efficiency of up to 99%. This proprietary charge pump circuit provides up to 99% conversion efficiency irrespective of input or output voltage. It also provides the benefit of lower EMI, lower output ripple, and no audible noise.

These benefits are achieved by the proprietary soft-charging, phase-interleaved architecture that operates as if it’s in a 100% duty cycle. Also, a capacitor is a much more efficient energy storage element—approximately 60 to 70× more efficient—than an inductor. This second-stage charge pump offloads the majority of the workload from the boost DC-DC converter, improves boost DC-DC efficiency, and achieves an overall higher system efficiency. The VOUT regulation is controlled by the boost stage. Figure 3 shows the simplified circuit diagram for this unique LED boost architecture.

circuit diagram of the LED boost architectureFigure 3 This simplified circuit diagram shows the unique LED boost architecture. Source: pSemi

This unique architecture has several advantages. The use of a highly-efficient charge pump circuit provides higher efficiency compared to the conventional LED boost architecture. This higher efficiency reduces the output voltage range of the boost circuit, impacting efficiency less when VOUT increases. Also, the efficiency is more consistent across input voltages (VIN) compared to a conventional LED boost, making run time much more consistent as the battery depletes. Figure 4 shows the efficiency as VOUT increases.

graph showing efficiency drop as VOUT increasesFigure 4 Notice the <0.5% efficiency drop as VOUT increases from 26 to 34V at the 5-W output power level. Source: pSemi

By reducing the output voltage on the boost circuit, a small and low-cost chip inductor can be used due to the duty cycle decrease. Because of the small chip inductor size, the inductor has a maximum 20V rating to avoid inductor internal leakage or shoot-through current, making it unsuitable for conventional LED boost for high VOUT applications. Compared to conventional LED boost architecture, the efficiency impact is smaller when inductor size is reduced.

The lower boost output voltage with this unique LED boost architecture allows the use of a synchronous converter, eliminating the need for an external diode.

The two-stage architecture steps up the voltage in multiple stages, and each FET in the charge pump and boost circuits only sees a small voltage step across drain to source. This multiple-step architecture allows the use of much lower voltage FETs, which reduces switching losses.

Only a small amount of the voltage is slewed across the inductor; the architecture uses a soft-charging charge pump that greatly reduces EMI and noise compared to a traditional single-stage architecture.

Figure 5 shows the efficiency comparison between the unique two-stage boost architecture and the conventional single-stage boost architecture. Figure 6 shows the power loss comparison.

graph of the efficiency of the two LED boost architecturesFigure 5 This graph compares the efficiency of the unique and conventional LED boost architectures. Source: pSemi

graph compares the power loss of the two LED boost architecturesFigure 6 A power loss comparison shows the unique and conventional LED boost architectures. Source: pSemi

VOUT for both devices is 34V, and both devices use a 4.7 µH inductor. However, the inductor used by the unique LED boost architecture is a chip inductor—DFE322512F-4R7M—available in a compact 3.2×2.5×1.2 mm case size. The conventional LED boost architecture uses a large wire-wound inductor—SPM5020T-4R7M—in a 5.4×5.1×2.0 mm case size.

Figure 7 shows the size comparison between the chip inductors and wire-wound inductors used in the efficiency measurements.

size comparison of a low-profile chip inductor and conventional wire-wound inductor

Figure 7 You can see the size difference between the low-profile chip inductor (left) and conventional wire-wound inductor (right). Source: pSemi

This comparison shows that the unique two-stage architecture has a large efficiency gain over the conventional single-stage architecture. The efficiency difference is as much as 8% in this measurement. An 87% efficiency at 5 W output power equals a power loss of 0.75 W, and a 93% efficiency at 5 W output power equals a power loss of 0.37 W. So, the unique two-stage architecture saves up to 0.37 W over the conventional single-stage architecture. This 0.37 W translates to a longer run time for mobile computing devices and a much lower temperature rise in the LED boost circuit.

New architectural approach

The LED backlight driver in an LCD display is a simple circuit, but it plays a critical role in system efficiency, battery run time, thermal management, and size. Unfortunately, many research efforts to improve the efficiency of this conventional circuit are focused on optimizing process technology instead of architectural innovation.

This article provides an example of how innovative architectural thinking can bring many benefits such as better efficiency, low operating temperature, smaller solution, and lower profile solution. Likewise, it helps lower EMI to reduce system interference and better integrate system protection features.

This article was originally published on EDN.

Jason Ngai is product line manager for power management at pSemi, a Murata company.

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