A signal integrity simulation and analysis reveals how the designers could violate common design rules to cut costs and still produce a working board.
EDN has long been a resource for engineers looking to improve designs. It’s long list of “how to” articles explain how to get designs to work and how to maximize performance. Some of the techniques presented in EDN articles show you how to boost signal integrity, reduce noise, or shrink power consumption. One of the ways we as engineers maximize performance is be adhering to establish design rules. But, what if conforming to those rules increases cost and makes your product unmarketable? That’s the dilemma the designers of low-cost embedded and consumer products often face.
To gain insight into once such product, we at Mentor Graphics have analyzed the BeagleBone Black, one of many low-cost microcontroller-based boards for makers and hobbyists. Our analysis shows how the designers of the “Black” made tradeoffs that many designers of industrial products need not make. Because the intrepid designers of the BeagleBone series published their designs, schematics, layout, and code for the rest of us to review and improve upon, we could analyze and simulate it from a signal-integrity perspective. Our analysis reveals stories about the tradeoffs its designers made to maintain performance while reducing cost—lessons we can apply to our own designs.
Originally released on 2013, the Black is part of a family of open-source hobbyist computers. It’s built around the Texas Instruments AM355x “Sitara” processor featuring 512 MB of on-board RAM, 2 GB of on-board flash storage along with Ethernet and HDMI ports. The Black (Figure 1) is shipped with Debian Linux in on-board flash memory, with a micro-SD card slot can be used to either re-flash the on-board memory or host an operating system directly. The Black has been superseded by newer models and is no longer a state-of-the-art device. It is still available for about $65 on Amazon.
The challenges of designing a low-cost system become apparent as soon as we look at the Black’s stackup (Figure 2). The board has only four routing and two plane layers, and the power-plane layer is chopped into pieces to accommodate the different voltages needed to run this board. “Best practice” high-speed design tells us that we should maintain a constant reference voltage for our signal as it travels from chip-to-chip, and that reference voltage should be ground where possible. Double data rate (DDR) memory has long used power-referenced signals to accommodate limited layer counts on dual in-line memory module (DIMM) devices; it’s clear we will have the same issue here, and we’ll have to contend with a reference plane that’s cut into pieces on top of that.
Note how thick the middle dielectric is in the stackup. The top and bottom are (electrically) rather far apart. The reason is clear enough: for the board to have adequate mechanical stiffness, it needs to be a certain thickness, and the large central core is the best way to do it. That means that we can’t count on embedded capacitance to decouple the power and ground layers, so any signal vias that traverse from top to bottom will need decoupling capacitors nearby to carry their return currents, and the effectiveness of those capacitors will be limited by the capacitor loop inductance.
The DDR3 interface (Figure 3) on the Black is incredibly simple; the processor talks directly to a single DRAM chip. From a schematic and routing standpoint, it doesn’t get much simpler than this. As it turns out – simple doesn’t necessarily mean easy. The Black’s DDR3 interface has some fascinating stories to tell about what it means to create a low-cost design. We’ll approach this from a Best Practice/ Design Guideline perspective – DDR3 defines a number of physical and electrical design targets that should be met for the design to work properly.
[Continue reading on EDN US: DDR3 design rules]
—Todd Westerhoff is the Product Marketing Manager for High-Speed and Analog/Mixed-Signal System Design for the Electronic Board Systems segment at MentorGraphics.