Low power and compact solutions meet embedded systems memory requirements

Article By : Maurizio Di Paolo Emilio

HyperRAM 2.0 offers HyperBus and Octal SPI interfaces and provides a read/write bandwidth of up to 400 MBps in DDR mode.

In 2014, Cypress unveiled the HyperBus interface which, leveraging upon the legacy features of both parallel and serial interface memories, improves the system performance, simplifies the design, and allows for a tangible cost reduction. Among the solution supporting HyperBus is HyperRAM, a novel technical solution able to achieve a throughput up to 333 MB/s, increased to 400 MB/s in HyperRAM 2.0. HyperRAM 2.0 is a high-speed, low-pin-count self-refresh dynamic RAM (DRAM) specifically designed for high-performance embedded systems requiring expansion memory, such as automotive, industrial, consumer and IoT applications. HyperRAM 2.0 offers HyperBus and Octal SPI interfaces and provides a read/write bandwidth of up to 400 MBps in DDR mode.


Through the cooperation with Cypress, Winbond Electronics has already launched 32Mb to 512Mb density products. Currently, products of 24BGA (6×8 mm2) with automotive-grade, WLCSP (Wafer Level Chip Scale Package) with targeting consumer wearable market, and KGD (Known Good Die) are all available.

Besides Cypress, other relevant leading MCU manufacturers such as NXP, Renesas, ST, and TI have already developed microcontrollers that support HyperBus interface, and their support is also expected in the future. At the same time, leading silicon IP provider such as Cadence, Synopsys and Mobiveil have also begun to provide HyperBus memory control IP, thus accelerating the time-to-market of products that include this memory solution.

The main benefits of HyperRAM, which can significantly improve the performance of end devices, are the following:

  • Low power consumption: this feature is achieved through the hybrid sleep mode (HSM) which draws only 45µW@1.8V and 55µW@3V (compared to the 2000µW@3.3V of a standby-mode SDRAM with the same capacity)
  • Reduced footprint: the low pin count allows to save precious space on the PCB
  • Easy control: with less active pins, the design is simpler without compromising the overall system performance.

Besides higher power consumption, low power SDRAM has a larger form factor than HyperRAM, and this does not make it an ideal solution when footprint and PCB area shall be reduced as much as possible. As shown in Figure 1, HyperRAM interface requires only 13 pins (DQ[7:0], RWDS, CS#, RESET#, CK and CK#), greatly simplifying the PCB design and the package size. Vice versa, a traditional SDRAM solution would require 38 pins and an area of 8×8 mm2 in a 54BGA package, while an LP SDRAM solution would require 41 pins and an area of 9×8 mm2 in 54BGA package. During the design phase of the products, more pins will, therefore, be available for implementing additional features, making the solution more cost-effective, as well.

Figure 1: Winbond HyperRAM block diagram

Another relevant feature of HyperRAM is that it is a self-refreshing RAM, meaning it can automatically return to the standby mode after completion of a read/write operation. This allows to reduce the effort of both system design and firmware development.

Regarding the use cases and industries which can benefit from this solution, they include all the applications that require low power consumption and high MCU computing power such as automotive, Industry 4.0, smart home, wearables, and IoT devices. Moreover, for battery-powered devices such as smart speakers and smart meters, low power consumption is crucial to achieve longer battery life.

Winbond HyperRAM is an ideal solution for embedded AI and image processing for classification, in which the device shall be made as small as possible, while providing enough memory space to support compute-intensive algorithms, such as face recognition, object detection, real-time image recognition and edge-computing.

“Regarding HyperRAM real application case, there are two main streams: one is accurate image recognition, and the other is voice recognition, both of them supporting AI models for voice or image”, said Jacky Tseng, DRAM Marketing Manager of Winbond in an interview with EEWeb.


SpiStack is a memory solution developed by Winbond, which is formed by stacking a NOR die and a NAND die into the same package, such as, for instance, a 64Mb serial NOR with a 1Gb QspiNAND die. This solution gives designers the flexibility to store code in the NOR die and data in the NAND die.

By stacking homogeneous or heterogeneous flash modules, SpiStack offers a wide range of memories with different densities for code and data storage, while providing designers with maximum storage flexibility for their design requirements. SpiStack memories require only 8 signal pins, regardless of the number of stacked dies. The active die can be switched through a simple software die selection command, providing a factory-assigned die ID number. The device can be clocked up to 104MHz, corresponding to a 416MHz clock rate under Quad-SPI. Moreover, SpiStack (NOR+NAND) supports concurrent operation, meaning with that one of the dies can be programmed or erased while the other one could be programmed/erased/read at the same and vice versa. For instance, an application could use the NOR die (SpiFlash, which offers better endurance and retention, and fast random access time) for storing the boot code and the application code, while multiple large-sized data (such as learning data for embedded AI and camera images) could be stored on the NAND die (QspiNAND). Multiple SpiFlash dies, each with density ranging from 16Mb to 2Gb, can be stacked with any combination of NOR and NAND dies.

As shown in Figure 2, SpiStack offers better read performance than serial NAND with continuous read. That’s because SpiStack supports concurrent operation: while a read operation is performed on one die, a write/erase operation can be performed on another die, without interrupting code execution for data updates.

Figure 2: SpiStack vs serial NAND w/cont. read performance

The main benefits arising from the adoption of the SpiStack solution are mainly three:

  • Small PCB footprint: this is a mandatory requirement for several applications, including IoT, wearable, consumer, and medical devices
  • Cost efficiency: the SpiStack solution allows to reduce both the number of components and the number of pins, simplifying the PCB layout and routing
  • High flexibility: the size of NOR and NAND dies can be combined to meet the specific application requirement. SpiFlash NOR flash is available with 16Mb, 32Mb, 64Mb, 128Mb, and 256Mb size, while QspiNAND is available with 512Mb, 1Gb and 2Gb size.

“The first benefit of our solution is it can provide a smaller form factor, which is crucial for applications such as IoT. The second is the cost, which can be reduced by putting together two memory dies into the same chipset. The third benefit is for customers, who can choose any available density of NOR and NAND dies”, said Wilson Huang, Flash Marketing Manager of Winbond.

Moreover, manufacturing costs can be reduced by integrating two chips in one package, and hardware compatibility is preserved by using standard package, an 8-pad WSON 8mmx6mm package (see Figure 3).

Figure 3: SpiStack WSON package

“We provide high-quality products because we use only mature and reliable technologies (46nm NAND and 58nm NOR). So, the quality is very good and our customers do not need to concern about quality”, concluded the speakers from Winbond.

This article was originally published on EEWeb.

Maurizio Di Paolo Emilio holds a Ph.D. in Physics and is a telecommunication engineer and journalist. He has worked on various international projects in the field of gravitational wave research. He collaborates with research institutions to design data acquisition and control systems for space applications. He is the author of several books published by Springer, as well as numerous scientific and technical publications on electronics design.


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