Low-power FPGAs deliver twice the I/O density

Article By : Susan Nordyk

General-purpose FPGAs in Lattice’s Certus-NX family deliver twice the I/O density per mm2 compared to similar FPGAs in packages as small as 6×6 mm.

Low-power FPGAs in Lattice Semiconductor’s Certus-NX family deliver twice the I/O density per mm2 compared to similar FPGAs in packages as small as 6×6 mm. Built using a 28-nm FD-SOI process, the devices offer up to 4 times lower power than FPGAs with comparable gate counts and up to 100 times higher reliability.

Lattice PR image of the Certus-NX FPGA

Certus-NX general-purpose FPGAs furnish up to 39,000 logic cells; 2.9 Mb of embedded memory; 56 18×18 multipliers; 192 programmable I/Os; one lane of 5-Gbps PCIe; two lanes of 1.25-Gbps SGMII; and two 12-bit, 1-Msample/s ADCs. Instant-on performance enables fast device configuration, with individual I/Os able to configure in just 3 ms and full device startup in only 8 ms to 14 ms, depending on device capacity. Strong ECDSA authentication and AES-256 encryption secure the devices’ bitstream against unauthorized access, alteration, and copying.

Lattice Radiant design software allows large complex user designs to be efficiently implemented on the Certus-NX FPGA family. The company also provides an extensive library of pre-engineered IP modules for Certus-NX.

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