Low power implementation techniques for ASIC physical design

Article By : Vipulkumar Patel & Rakesh Gosai

Learn about low power implementation techniques that can be used in physical design implementation in an ASIC.

In the semiconductor domain, the operating frequency of devices and the number of transistors in a single module increase over time. In this article, we will look at widely known low power implementation techniques which can be used in physical design implementation in an ASIC. There are three major power losses in a CMOS device: dynamic power, static power and short circuit power.

Total power consumption in a CMOS device is as follows:

Power Total = Power Dynamic + Power Static + Power Short-circuit               Equation (1)

A CMOS device has very low static power consumption which occurs when all the inputs are at some valid logic level and the device is not switching.

Static power consumption is a function of supply voltage, transistor threshold voltage and transistor size. When operating at a higher frequency, dynamic power consumption contributes significantly to overall power consumption and is given by:

Power Dynamic = a F Cload VDD2                 Equation (2)


Cload = Load capacitance of the CMOS

VDD = Supply voltage

F = Operating frequency at which the transition happens

a = Switching activity constant

From equation (2), we can conclude that dynamic power dissipation is directly proportional to operating frequency and supply voltage of the devices.

Now, the first component is the frequency of the design, but we can’t reduce the operating frequency since digital devices continue to become faster. So, we need to play with the clock network to save the power. To save the power from the clock tree, the designer uses the clock gating techniques wherein a special enable signal is applied on the clock gating cells to turn on the clock for the specified group of flops – this helps reduce dynamic power consumption.

The second component to save power is the supply voltage of the chip. There are various techniques for saving the power with the help of supply voltage.

  • Multi VDD
  • Lever shifter insertion for cross domain
  • DVFS (dynamic voltage frequency scaling)
  • Multi Vt
  • Power gating (power shut off)

Let’s discuss in detail the implementation technique to save power with supply voltage.

1) Multi VDD

Multi VDD technique is used for saving the dynamic and static power of the design. Here, the chip is implemented with the different supply voltages. Different functional blocks run at a different supply voltage. We can save the power losses by reducing the supply voltage for standard cells and memory elements of the design.

In multi VDD technique, different power domains are defined based on the criticality of the design. Here level shifters are used for the signal coming from low voltage power domain to high voltage power domain and vice versa. At the netlist level, the design code will be written in UPF and CPF power format, based on which we can develop the power structure for the design.

2) Level shifter insertion for cross domain

In multi VDD design, level shifters are used. A level shifter is the digital component which is used to convert the signal from one to another voltage level (from low voltage level to high voltage level and vice versa).

There are some special placement guidelines for inserting the level shifter across the different power domains in the design. The level shifter should be placed in the destination domain of the design. There is one disadvantage of inserting the level shifter – it occupies area in design. But, at the same time, inserting the level shifter will help in saving the power of the chip.

There are two types of level shifters.

  • High to low voltage level shifter

It only introduces buffer delay, so it’s impact on timing is minimum. The below figure shows a high to low level shifter.

Figure 1
A high to low level shifter

  • Low to high voltage level shifter

Low voltage swing input signal would not necessarily be strong enough to turn the input transistor fully on. This could lead to an unacceptably long rise time or fall time. It may cause higher switching current and reduce the noise margin. The below figure shows a low to high level shifter.

Figure 2
A low to high level shifter.

During the placement stage, special care needs to be taken for the low to high voltage level shifter.

3) DVFS (dynamic voltage and frequency scaling)

In the DVFS technique, operating voltage, as well as the frequency, change dynamically as per the different operating modes of the design. By varying the voltage with frequency, we can reduce the power consumption. When a high operating speed is required, the supply voltage is increased to attain higher frequency of operation with the penalty of increased power consumption.

Dynamic voltage and frequency scaling is a widely accepted power and energy reduction technique used for a wide range of computing systems, microprocessors, etc. Lowering the supply voltage can reduce power consumption because of the quadratic relation between power and supply voltage. Since this technique optimizes both voltage and frequency, it is highly effective for static and dynamic power consumption. The below figure shows power saving achieved by using variable supply voltage.

Figure 3 A power savings is achieved by using a variable supply voltage

4) Multi Vt

This technique involves implementing the design with a multi-threshold voltage standard cells library to save power in the design. Libraries are offered in standard Vt, low Vt, and high Vt forms, independent of each other. These libraries are used for power and timing optimization.

After the completion of routing in physical design flow, power recovery can be done by Vt swapping in the non-timing critical path, by swapping the low Vt cells to high-threshold voltage cells during the signoff stage in prime time.

Recently multi Vt synthesis flow has become more common in lower technology nodes. In the ASIC design flow, a primary standard Vt library is used for initial synthesis. Multiple threshold cells are used for the next iteration of optimization and synthesis.

5) Power gating (power shut off)

The internal leakage power of the CMOS circuit can be reduced by shutting down the block/module for a particular interval of time by applying a specific signal. Power dissipation can be saved by using the power gating techniques which could be inserted into the netlist.

In this technique, the blocks are placed in the shut down mode when the function is not active and are turned on as and when required. This enabling and disabling of logical functionality of the system is controlled by applying some special signal (pull up or pull down) on the cells (power gaters). The addition of these special cells (gaters) occupies more area.

These gaters are also known as sleep transistors which are used as switches to shut off the power supplies to a part of the design and connect permanent power supply to the circuit power supply. A PMOS sleep transistor is used as a “header switch” for the VDD supply and an NMOS sleep transistor controls the VSS supply and is known as a “footer switch.”

Power shut-off (PSO) can be implemented in two different manners: on-chip power shut-off and off-chip power shut-off. The power switches are within the SoC in on-chip PSO; power switches are external to the chip in off-chip PSO.

PSO can likewise be either fine or coarse gating, referring to the size of each block constrained by a single power switch . With fine power gating procedure, we can save the power by shutting down the individual blocks without closing off the power to different blocks which keep on working. This will help to reduce leakage power of the CMOS. With coarse-grain technique, a single sleep signal can power down the entire region. This helps in  reducing leakage power in the standby mode.

We need an isolation cell for the signal coming from the power gated block as shown in the below Figure 4.

Figure 4
An isolation cell is needed for the power gated block signal

This isolation cell is always a ‘power up’ cell and it prevents any unknown logic level to reach to the ‘always on’ logic.

A retention register is also needed while doing power gating to save content of a power gated block before it switches off. As shown below in Figure 5, the retention register contains one shadow register besides the main register. The shadow register is powered by the ‘always on’ supply which stores the logic value of the block being power gated when “SAVE” is asserted high. It restores this logic value to the main register when “RESTORE” is asserted high.

Figure 5
Retention register contains one shadow register along with the main register

In this paper, various low power implementation techniques have been discussed. Adopting a particular technique depends on the design complexity and components of power dissipation to be reduced. One also needs to consider timing penalty, area penalty and implementation complexity of each of the above discussed techniques before adopting them.

In general, Multi VDD and DVFS techniques are used for reducing dynamic and static power consumption whereas multi Vt and power gating techniques are mainly used for leakage power reduction.


  1. C. H. Hsu, Compiler-Directed Dynamic Voltage and Frequency Scaling for CPU Power and Energy Reduction, Ph. D. Dissertation, the State University of New Jersey, USA, 2003
  2. Diary R. Suleiman, Muhammed A. Ibrahim, Ibrahim I. Hamarash, Dynamic voltage frequency scaling (DVFS) for microprocessors power and energy reduction
  3. Low power methodology manual book study

Vipulkumar Patel is a senior physical design engineer at eInfochips with 7 years of experience in the  VLSI/ASIC field. 

Rakesh Gosai is a senior physical design engineer at eInfochips with 4 years of experience in the ASIC field across different nanometer technology nodes (7 nm, 16nm).

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