PCB manufacturing yields opportunities to maintain signal integrity and other performance characteristics without expensive materials.
When reading and studying the multitude of opinions available in articles and on the internet, it’s easy to assume that there is consensus among those in the know that the days of using traditional low-cost PCB materials for next-generation high-speed design are dead and gone. Then there is this notion that the requirements of modern technologies such as PCIe 5.0 and beyond have pushed the boundaries of board design and manufacture toward the brink.
Taking a closer look at the materials and methods involved, though, provides new hope that although we are indeed sprinting ever closer to the brink, there are some key adjustments that we can make, which may allow us to stop short of crossing it, at least for now.
Next-generation PCB materials at a cost
While it’s true that the use of next-generation materials will allow for easier incorporation of new technologies into designs, this increase in capability and performance comes at a literal cost: it is much more expensive to manufacture a PCB using exotic materials. The increase is likely to be in the neighborhood of 100% (2×) or even more, depending on the design specifics.
Some companies are more willing to make this quantum leap because their systems and designs can accommodate the use of exotic materials and absorb the extra costs associated with their use. However, there are many others who are subject to tighter design and budgetary constraints, which would make the transition more difficult.
For this reason, Intel engineers have worked hard to study the various factors involved and provide a number of approaches that will allow designers to build next-generation technology into their designs using lower cost, current-generation PCB materials and processes.
Cost is not the only consideration
When incorporating next-generation technology into your designs, some increase in manufacturing costs is inevitable. Our research has determined, though, that there are a number of variables that can be managed to keep the increase to as little as 30%.
Following are some of the more easily applicable insights that have been gleaned from the research that we performed. As you read, though, it is important to keep in mind that this approach is not a panacea—there are trade-offs to consider at every level, and while overall cost is important, it is only one of the factors that has to be considered.
When manufacturing PCBs, there are any number of variables that have to be taken into account. However, our efforts have determined that the most benefit comes from focusing on four of these design variables in particular: dielectric material, surface roughness of the copper, oxidation process, and optimization of the stackup. For each design variable, we also list the options that the industry can put efforts in, and deliver cost-effective solutions.
Traditional FR4 dielectric materials use an epoxy-based resin with E-glass reinforcement system to keep the cost down. Exotic dielectric materials typically require the use of a more expensive PPE/PPO-based resin system and/or low-Dk glass for better performance, increasing the overall manufacturing cost.
Option: Newer production methods have been developed which combine epoxy with the PPE/PPO-based resin, resulting in a finished board with performance characteristics that can meet the performance requirement but at a lower manufacturing cost.
In an ideal scenario, high-speed signals would traverse paths made from copper that have no surface roughness. Unfortunately, in the real world, using ‘smooth’ copper is not a possibility as other materials will have difficulty adhering to it and the PCB will delaminate and fall apart. For this reason, some level of roughness is inherent to all of the copper used in PCB manufacturing. For boards with higher electrical performance and lower loss requirements, manufacturers use copper with a lower (smoother) profile. The drawback is that these materials are more expensive.
Figure 1 Higher copper roughness impedes current flow, resulting in higher losses. Source: Intel
Option: The use of a newer type of copper foil, commonly referred to as RTF2, is gaining popularity in the market. RTF2 is a copper foil with a non-uniform roughness profile whose performance is close to hyper very low profile (HVLP) copper foil but can be manufactured at a lower cost. The next generation of RTF2 copper foil is also being investigated to achieve HVLP-like performance with minimum cost increase.
In PCB manufacturing, a surface oxidation process is typically required to promote adhesion between core and prepreg layers for optimal bonding. A precise balance must be struck during this process because while increasing the surface roughness of copper foil will help to boost adhesion, it can have a significant negative impact on the copper profile and thus on signal integrity. An imprecise or unnecessarily aggressive oxidation process can nullify the improvements gained by paying for better-performing, lower-profile copper foils by over-roughening them prior to bonding.
Option: Low-etch oxidation chemistry and adhesion promoters—which reduce the requirement for roughening of the copper surface while maintaining the desired bonding strength of the PCB—are being developed and adopted by the industry. Less surface oxidation also decreases the potential negative impact on signal integrity, making this approach a win-win.
In some ways, proper determination of the PCB stackup is the low-hanging fruit of the performance optimization and cost minimization process because, well, thickness matters.
Figure 2 The right stackup can help minimize PCB losses. Source: Intel
Option: When taking a careful look at the signal loss characteristics of the more common core/prepreg layer thickness options, it becomes clear that losses can be minimized simply by taking the time to determine the right stackup. In one test performed by Intel engineers, it was found that, when measuring signal loss, a 5/6 stackup—5 mil core thickness and 6 mil prepreg thickness—outperformed a 3/9 stackup by more than 15% using the same substrate and copper profile.
Of course, this approach is not a slam dunk, as changes to the stackup can have a negative impact on routing density and noise coupling. However, it does serve to emphasize that careful selection of the stackup and its signal integrity implications are a critical step in the performance and cost optimization process.
Collaboration with academia
As mentioned above, Intel has undertaken this research effort as a means to provide alternatives for companies which may find it difficult—or even impossible—to build the next-generation materials into their systems and designs. But even with the amount of resources that Intel has, there are gaps in the research and development that we simply cannot fill on our own.
So, academia must be involved in these efforts at all levels. Several evolutionary steps forward have been made in this field by industry experts and academicians working together with the common goal of identifying, studying, and solving the problems that plague PCB manufacturing. This collaborative approach is key to ensuring that our industry continues to innovate and grow many years into the future, just as it does today.
Editor Note: This is the first article in a series about high-speed interconnect design. Stay tuned for more information on CXL protocols, PCIe 4.0 routing, and integrated Ethernet in Snow Ridge in the following articles.
This article was originally published on EDN.
Jeff Hockert is a senior marketing manager in the Technology Leadership Marketing Team at Intel.