Maintaining precise timing across large, heterogeneous Synchronous Ethernet networks

Article By : Kimberly Gerber

What is SyncE, and why is it so important to modern communications networks?

What is SyncE, and why is it so important to modern communications networks? The short answer is that it’s shorthand for Synchronous Ethernet. The longer answer is that it’s a variant of standard Ethernet that allows all nodes within a network to work in synchronization, despite widely different propagation delays.

It does this using a method for transferring frequency information over Ethernet’s physical layer across a network that is traceable to a reference clock. In doing so, SyncE’s ability to provide frequency synchronization across large, widely-distributed networks, has made it a widely used technology in both wireline access and wireless data backhaul networks. And, as 5G networks continue to roll out, SyncE will be there to support the many applications that require an accurate frequency reference.

Synchronization evolution
Ethernet’s low cost and simplicity have made it the dominant medium for data transmission as telecom and wireless providers shift from traditional voice networks to what has become predominantly IP-based packet data traffic. To keep up with the growing volumes of packet data, carriers have been gradually replacing much of their older time division multiplexing (TDM) synchronous optical networking (SONET) and synchronous digital hierarchy (SDH) networks with packet-switched networks based on Ethernet.

These IP/Ethernet-based networks offer lower cost and higher capacity, along with the ability to carry different types of services over the same network. Problems do arise, however, since conventional Ethernet communications are asynchronous, which poorly serves applications like high-quality voice conferencing over IP, better cellphone handoffs, and advanced sensor networks that require low latency and real-time communications.

To solve this problem, SyncE replaces the line signals at the physical layer used by traditional TDM systems with a TDM-like synchronized timing technology that’s compatible with Ethernet’s packet-based protocol. For scalability of large networks with many end points, there is an advantage to distribute synchronization from a centralized location using a primary reference clock (PRC) to the edge of the network.

SyncE supports creation and distribution of high-quality timing references (such as a PRC) across wired networks and out to the edge of the wireless baseband unit for wireless networks. SyncE eliminates the retiming effort by transmitting the timing frequency over the physical layer along with the data. It is important to note that SyncE is capable of frequency synchronization only, passing the frequency information from node to node in the network. This is different from time synchronization, which includes both frequency and phase distribution in packet-based networks such as precision time protocol (PTP).

SyncE accuracy requirements
SyncE’s network synchronization mechanism is based on a clock hierarchy, with the highest accuracy clock at the top. In virtually all SyncE networks, this is a PRC, which has a precision of 10e-11. This reference can be derived from either a local ultra-stable timing source or, more often, a GPS signal. The next level down is the synchronization supply unit (SSU), also referred to as building integrated timing supplies (BITS). The SSU level requires a holdover feature that allows the unit to maintain timing for some period in case there is a loss of the PRC input in the network. We’ll discuss holdover in further detail later in this article.

The third level is the Ethernet equipment clock (EEC), which also requires holdover, but the accuracy of the holdover is less stringent than the level above. This third level is the SyncE clock, which is implemented with a phase locked loop (PLL) capable of tracking a local backup oven-controlled crystal oscillator (OCXO) or temperature-compensated crystal oscillator (TCXO) reference with frequency stability of +/-4.6 ppm or better.

Keep in mind that the entire network will have PRC (10e-11) accuracy when the primary reference link is available. The SyncE timing distribution provides a PRC traceable clock to each node during normal SyncE system operation. SyncE is sometimes mistakenly thought to have +/-4.6 ppm timing accuracy, but this is just the free-running accuracy of the EEC clocks. Applications such as mobile networks require accuracy in the neighborhood of +/-50 ppb. When the system is locked and synchronized by a PRC, it should deliver ppb accuracy or better. Only when the device loses synchronization would it fall back on the EEC local OCXO/TCXO reference clock accuracy. Figure 1 provides a simplified illustration of the +/-100 ppm to +/-4.6 ppm difference between conventional Ethernet and SyncE timing.

diagram of interface differences between native Ethernet and synchronous EthernetFigure 1 This diagram shows interface differences between native Ethernet and synchronous Ethernet.

SyncE clocking challenges and ITU standards
International standards for implementing SyncE are defined by the International Telecommunication Union Telecommunication (ITU-T) network interoperability governing body. This group has written interoperability agreement standards that equipment manufacturers must meet to be considered compliant. The following standards pertain to SyncE compliance:

  • G.8262 Clock Requirements: Defines timing characteristics of synchronous Ethernet equipment clocks (EECs),
  • G.8262.1 Clock Requirements eEEC: Defines timing characteristics of synchronous enhanced Ethernet equipment clocks with tighter requirements focusing on 5G.

The above-mentioned G.8262 and G.8262.1 standards include various jitter and wander requirements that the SyncE clock must be capable of meeting for compliance. Unfortunately, physical layer clocking as implemented in SyncE suffers from jitter and wander, which diminishes the quality and reliability of the clock going through the networks.

As a result, the SyncE clock has a restricted allocation of the overall system-level timing budget. In this context, jitter is defined as phase variations above 10 Hz bandwidth and wander is defined as the variations occurring at a frequency below 10 Hz. Using 10 Hz as the dividing line between jitter versus wander is an arbitrary convention that has been used in the telecom industry for many years. In truth, jitter and wander are both phase variations, but their effects in the network are different.

Excessive jitter causes bit errors, which may result in dropped or lost packets in the network data. Wander affects the ability of the clocking function to lock and track the upstream timing reference and will impact the distribution of the clock reference passed down through the network. In each of the downstream clock devices in the network, the device is locked to the frequency of the primary reference clock by recovering a clock from the incoming physical layer signal.

The ITU-T standards outline the testing and expected requirements for a clock to be SyncE compliant. G.8262 offers two different bandwidth options. Option 1 (1-10 Hz) is the bandwidth used in synchronization networks default value in Europe, optimized for the performance requirements of the equipment in a 2048 kbit/s hierarchy. Option 2 (0.1 Hz) is the bandwidth used in the United States, optimized for a 1544 kbit/s hierarchy.

It is important to choose a high-quality clock that can meet these standards to ensure proper operability of SyncE. It is not as simple as having a clock that is accurate to +/-4.6 ppm; there are several other performance metrics the clock must meet to ensure proper operability of synchronization. The following are some of the key clock-level tests.

Free-run accuracy
The accuracy of the clock output when it is not driven by an upstream reference should be equal or better than +/-4.6 ppm over a time period of one year. This is a very accurate clock relative to the clock accuracy for traditional Ethernet (+/-100 ppm).

The clock constantly calculates the average frequency of the locked reference. If the reference fails and no other references are available, the clock goes into holdover mode and generates an output clock based on a calculated average value. Holdover stability depends on the frequency stability of the oscillator used as the PLL master clock.

Input monitoring
The clock must constantly monitor the quality of the inputs. If the input deteriorates (disappears or drifts in frequency), then the clock switches with a “hitless switch” to another valid input with very little phase disturbance on the output. Maximum limits are defined for compliance.

SyncE jitter testing
Jitter is present at every network data interface. High-quality jitter attenuator clocks, such as the Silicon Labs Si539x/4x devices, have low intrinsic jitter. These jitter attenuator devices are robust and jitter-tolerant compared to other devices and are fully capable of meeting the SyncE compliance requirements.

  • Jitter generation: The clock must not exceed the limits of the given mask. These are defined based on the interface of 1G, 10G, and 25G lane rates. To help networking equipment meet this challenge, Silicon Labs offers jitter attenuators that generate <100 fs jitter in the 12 kHz-20 MHz integration band. We will use one of these devices, the Si5395, to demonstrate how SyncE’s inherent characteristics can be mitigated.
  • Jitter tolerance: This test verifies the robustness of the clock device to jitter applied to the input. Figure 2 shows the Si5395 jitter attenuator results for a 25G jitter tolerance test in which a 25 MHz frequency modulated signal is generated and placed on the input clock. For each of the modulation frequencies proposed by the standard, a modulation deviation sweep is performed until one of the device alarms is triggered, indicating failure. This figure shows that the Si539x clock exceeds the minimum jitter tolerance requirements.

graph showing jitter attenuator results for a 25G jitter tolerance testFigure 2 This graph shows results for jitter tolerance EEC testing for G.8262 compliance.

SyncE wander testing
Each downstream clock device is locked to the frequency of the PRC by recovering the clock from the incoming physical layer (SyncE). But the process of recovering and regenerating the clock reference could be a source of wander. To prevent this, a SyncE-compliant PLL is responsible for filtering wander accumulated along the synchronization chain. This is achieved with a PLL loop bandwidth below 10 Hz. The standards limit how much wander is transferred across the PLL and how much wander it generates given a wander-free input.

Wander is measured against an external reference clock, which is in direct communication with the master reference clock signal. The fundamental measurement for wander is time interval error (TIE). This represents the clock signal under test relative to the reference. TIE is used to compute several other measurements, such as the following:

  • Maximum time interval error (MTIE) is the peak to peak variation of TIE. It increases monotonically with the observation interval. This provides the long-term behavior and stability of a clock and is insensitive to high-frequency noise.
  • Time deviation (TDEV) is effectively a spectral analysis of the TIE plot as a function of the observation interval “tau.” It is calculated by taking the RMS value of TIE after applying a filter bandwidth that varies inversely with the observation interval. To get accurate results for TDEV, the measurement period should be at least 12 times the maximum observation interval required.

Much of the SyncE test procedure involves various types of wander measurements, and the results in some of the tests can depend greatly on the quality of the backup reference (TCXO/OCXO) supplied to the clock device. The following are the key wander tests and their purpose for SyncE compliance.

Wander generation
The intrinsic wander of the clock can be measured when a clock is locked to a wander-free input. There are strict limits on how much wander the SyncE clock can introduce, which is defined by the MTIE and TDEV masks. Figure 3 shows the MTIE and TDEV masks and the measured results from the Silicon Labs Si5395 jitter attenuator clock.

Wander Generation Results and Masks for MTIE and TDEVFigure 3 This graph shows the MTIE and TDEV masks (dashed lines) and measured results from the Silicon Labs Si5395 jitter attenuator clock.

Wander tolerance
Wander is injected into the input of a noise-free input clock signal to simulate the worst levels that a synchronization-carrying interface could experience. This test verifies that the clock can manage the incoming wander by monitoring the clock device alarms. A mask is given in terms of both MTIE and TDEV to qualify the limits of the wander on the output for the maximum given wandering input.

Wander transfer
Wander transfer measures how much wander is passed from the input of the clock device to its output. Ideally this will be limited and managed by the device’s PLL filtering circuits.

Phase transient testing
Phase transients can occur when the input reference is lost and the PLL switches to a backup reference, or switches into holdover if a backup reference is not available. The standards specify maximum limits on these types of transients.

It is important for network equipment designers and users to understand the end application requirements before selecting one synchronization method over another. SyncE provides benefits to many expanding Ethernet networks by enabling a centralized synchronization source to be transported across the network. This physical layer distribution method provides ppb level frequency accuracy across the network. It can be used to provide large wired/hybrid networks with the frequency synchronization required for demanding real-time applications.

It’s important to remember however, that SyncE only provides frequency synchronization and has limitations in that phase data is not propagated. In addition, SyncE does not have a mechanism for transmitting time of day information. Time (frequency and phase) synchronization across packet based Ethernet networks can be done using PTP, which is a two-way message protocol used to synchronize time of day between master and slave ports across an Ethernet network.

Kimberly Gerber is a customer applications engineering manager for timing products at Silicon Labs.

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