Making measurements with your mind’s eye
Article By : John Dunn
There are always going to be situations where the only real measurement tool you have available is your own mind's eye.
Do you ever envy the engineer who has access to lots of fancy and expensive test equipment? Do you ever come across a situation where you “would if you could” measure some parameter that’s affecting the item sitting on the bench in front of you but for which physical access issues somehow make that impossible?
Let’s face it, there are always going to be situations where the only real measurement tool you have available is your own mind’s eye. With that in mind (pun intended), please consider the two following examples.
Case 1
Some while ago, I wrote about reducing pulse jitter in a troublesome switch mode power supply. I shunted the Ct timing capacitor of the supply’s PWM chip with a series RC pair.
Figure 1 Add an RC pair to the Rt Ct.
The reason that worked was that the resistive loss of the series RC pair lowered the Q of an LC circuit that was comprised of the Ct capacitance itself versus whatever inductances were connected to it. Those inductances were that of the capacitor itself plus that of the wiring, even as physically short as that wiring happened to be.
Even though I couldn’t get a dependable look with the available scope and scope probes, I knew what had to be going on there. I knew that there had to be some high speed-ringing going on involving Ct in response to pulses that were coming from the power MOSFET’s switching. By adding an RC pair across Ct, I introduced damping that quelled troublesome ringing that I couldn’t actually see.
I posted links to that Living Analog item in LinkedIn and in one LinkedIn group, I got the following rather derisive comment: “This is an example of the try-it-and-see approach; an approach I used when designing circuits in the 1960’s.”
This wasn’t something from “the magic capacitor” school of engineering. I had visualized what was going on with Ct and on that basis, I found a remedy. I had a visualization in my mind’s eye of what was afoot.
Case 2
Several decades ago, I designed an AGC-controlled sine wave oscillator. It was a Wein bridge circuit that was set up to run on a single rail voltage of +15V. This was its schematic. It delivered its output at 1V peak-to-peak.
Figure 2 This sine wave oscillator is a Wein bridge circuit set up to run on a single rail voltage of +15V.
U2a served as a precision rectifier as part of the AGC loop. At the cathode of D1, there was half-wave rectification of the output sine wave, but by including the 20 k-ohm resistor R6, the resulting current being delivered to the summing junction of the U1b error amplifier was equivalent to full-wave rectification.
The underlying concept is merely this:
Figure 3 Full wave is achieved as the sine wave is added to the half-wave rectification waveform.
A colleague told me I was wrong. His attitude was that a half-wave rectifier is a half-wave rectifier, period, and that the 20 k-ohm resistor wasn’t serving any useful purpose and should be removed.
I didn’t have any version of SPICE available to me at the time and there was no way to physically wrap a current probe around any of the circuit traces. As a result, I could not demonstrate my full-wave claim and therefore, I could not convince my erroneous colleague of what was actually happening.
Today however, by using SPICE, we can see what we once could not, which is that with 2:1 scaling at the error amplifier’s summing junction (R11 and R13 in the SPICE model below), we get full-wave behavior as the sine wave itself is added to the half-wave rectification waveform.
Figure 4 The simulation shows that with 2:1 scaling at the error amplifier’s summing junction, we get full-wave behavior.
The version of SPICE that I was using did impose one problem on me though. The junction FET (JFET) was a 2N4391 in the real unit, but that device was not available as a modeled part in this particular SPICE package. The one and only JFET model that was available was used instead, but the 1K feedback to the JFET had to be raised to 10K in order to get this SPICE simulated oscillator to actually oscillate.
If you can forgive that, you’ll see the full-wave waveform of the current flowing into the error amplifier’s summing junction. Here again, I made this circuit work by visualization in my mind’s eye of what was going on.
Sometimes, the grey matter between your ears will allow you to do stuff that Tektronix, Agilent, Fluke, and other instrument makers just can’t match.
John Dunn is an electronics consultant, and a graduate of The Polytechnic Institute of Brooklyn (BSEE) and of New York University (MSEE).
Related articles:
- Rt Ct Snubber
- Designing sine-wave oscillators
- Test 18-bit ADCs with an ultrapure sine-wave oscillator