Cut emissions with integrated data, power isolation: Step 4

Article By : Anand Reghunathan, Koteshwar Rao, Anant Kamath

One way of minimising the current loop is to include a high-voltage capacitor from side 1 to side 2, and place it as close to the IC as possible.

« Previously: Minimise emissions with integrated data, power isolation: Steps 1-3

As we discussed earlier, the common-mode current from side 1 to side 2 and a large return loop are the main causes of emissions in isolated systems. One way of minimizing the current loop is to include a high-voltage capacitor from side 1 to side 2, and place it as close to the IC as possible (figure 8).

Figure 8: A side 1 to side 2 high-voltage capacitor reduces the common-mode current-loop area.

The capacitors suitable for such use include high-voltage Y2 capacitors (surface-mount device [SMD] or leaded with appropriate creepage/clearance levels) commonly used in power supplies. Using Y2 capacitors on the printed circuit board (PCB) introduces lead inductances on both sides of the capacitor – along with its own parasitic inductance – making the capacitor ineffective at frequencies higher than 200MHz. One way to create a low-inductance capacitance is by overlapping internal PCB layers.

Consider a four-layer PCB with the top layer for the signal, layer 2 for ground, layer 3 for VCC and the bottom layer for the signal. Because of system isolation, PCB layers are separated into two groups: side 1 layers (forming Signal1, GND1 and VCC1 layers) and side 2 layers (forming Signal2, GND2 and VCC2 layers). Extending the internal reference layers (GND and VCC) on either side of the isolation barrier (Figure 9) creates an overlap of internal layers.

This overlap area, formed by the extension of the GND1 and VCC2 layers with FR4 material between them acting as a dielectric, creates stitching capacitance between GND1 and VCC2. For fast transient common-mode currents, both GND and VCC points are considered to be the same references (similar to AC analysis). Hence, interlayer stitching capacitance forms between the reference points of side 1 and side 2. Figure 10 is a 3-D representation of the interlayer stitching capacitance created in a four-layer PCB.

Figure 9: Cross-section view of PCB layers with interlayer stitching capacitance.

Figure 10: 3D diagram of PCB layers with interlayer stitching capacitance.

By applying Equation 1, you can calculate the equivalent capacitance formed between the sides as:

PowerDataIsolation_TI_E1_201703 (cr)

where ε = ε0 εr. Ci is the interlayer stitching capacitance, ε0 is the absolute permittivity of air (8.854 pF/m), εr is the relative permittivity of the dielectric (4.2 for FR4) A is the overlapping area and d is the distance between the GND and VCC layers.
From Equation 1, solving for interlayer stitching capacitance Ci for the PCB in figure 9 would produce an approximate value of 30pF.

Implementing a stitching capacitance across the isolation barrier with appropriate spacing is necessary to meet the system’s overall isolation performance. End-equipment electrical safety standards and working voltage conditions determine these spacing requirements. Most system standards with functional or basic isolation do not have a minimum spacing requirement between the side 1 and side 2 layers on the same plane or on different planes. For such systems, it is best to use the lowest spacing between the overlapping area to achieve the highest capacitance value. You must also consider the working voltage expected across the barrier and the dielectric strength of the insulation material.

Standards for safety systems and systems with reinforced isolation may require a minimum spacing between side 1 and side 2 layers on both the same plane and on different planes. Allowing 0.4mm spacing for <300VRMS systems and 0.6mm spacing for 300VRMS to 600VRMS systems meets most standard requirements. Besides these spacing requirements, standards bodies prescribe requirements on temporary overvoltages and surge voltages. For example, International Electrotechnical Commission (IEC) 66010-1 mandates a 5s withstand test of 3,510VRMS and a surge or impulse test of 6,400VPK for reinforced isolation between 300VRMS and 600VRMS mains voltage. You must design the interlayer spacing to withstand these voltages, keeping in mind the dielectric strength of the insulation. For example, FR4 has a dielectric strength of 20kV/mm.

Figure 11 shows the reduction in radiated emissions with the use of an interlayer stitching capacitance. With just a 30pF capacitor between the two sides, you can attain an improvement of 10dB to 20dB across frequency. Higher stitching values can provide progressively higher attenuation in emissions.

Figure 11: The ISOW7841 with and without a 30pF stitching capacitance at a 5V input and 80mA load current.

Apart from maintaining the spacing across the barrier, you must take extra care at the edges of the PCB. At the edges, the planes may be exposed to air; because opposite voltages come close to the edge of the board, these opposing voltages could lead to electric field stress and then air breakdown along the edge. Sharp edges and corners can also contribute to the air breaking down further because they increase the intensity of the electric field in the vicinity of the sharp edge, leading to a breakdown path for high-voltage impulse tests. To avoid such scenarios, pull in the inner layers at the edge of the PCB and modify sharp edges into triangle-cut shapes, which will spread the charge density. Figures 12, 13 and 14 show an example of such an implementation. Rounding the corners and planes can also further enhance the solution.

Figure 12: Pointed sharp edges close to the PCB edge.

Figure 13: Stitching plane pulled back from the edges.

Figure 14: Triangle corners implemented to enhance high-voltage performance.

While the inner layers of the PCB completely surrounded by dielectric allow relatively lower spacing (as discussed above), the top and bottom signal layers need to maintain much higher spacing. This spacing is based on the expected temporary overvoltage, impulse voltages, and environmental conditions such as altitude and pollution degree.

Next: The final steps: 5-7 »

Leave a comment