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Mixed-signal printed circuit boards (PCBs) present unique challenges in high-performance applications, such as vibration analysis and other multi-channel data acquisition systems. Nonlinear signal-chain elements introduce unwanted harmonic distortion, increasing the magnitude of the input signal’s harmonic content. Meanwhile, multiple switching elements produce intermodulation artifacts that present themselves as frequency spurs asynchronous to the signals of interest. The noise and distortion degradation introduced by these nonidealities can significantly limit the overall performance of applications aiming for high resolution at high bandwidth.

In this article, we’ll explain how clocks and other switching elements produce intermodulation artifacts, analyze their impact on high-performance signal chains, and present PCB guidelines and bench setup techniques to minimize their effect.

**Clock intermodulation effects in mixed-signal systems**

Clock signals are square waves used to provide a timing reference for many integrated circuits, predominately data converters, microcontrollers (MCUs), and digital signal processors (DSPs). While an ideal sine wave comprises of only a singular, fundamental frequency with no harmonics, an ideal square wave has an infinite number of high-energy harmonic components, as expressed by the Fourier series (Equation 1):

**Figure 1** shows the frequency spectrum for an ideal clock source with a 50% duty cycle (a perfect square wave). The largest tone in the spectrum represents the fundamental frequency (*f*) and is followed by several odd harmonic frequencies (3*f*, 5*f*, 7*f*, etc.).

**Figure 1 **The frequency spectrum plot of an ideal square wave has all the odd harmonics.

For many precision analog-to-digital converter (ADC) applications, these high-frequency harmonics will occur outside of the signal bandwidth of interest and have little to no effect on measurement accuracy. Most mixed-signal systems contain at least two independent clock sources, however: one for the data converter and one for the MCU or DSP. Additional clock sources may be required for digital interfaces, supporting peripheral circuitry and other data converters in the system. Each of these clock sources will contain their own fundamental frequency and an infinite number of harmonics. More than likely, these clock sources will share a common ground or power supply, and physical PCB constraints may prevent you from isolating these clock sources enough to minimize coupling. If any two or more of these fundamental or harmonic frequencies occur close together, they can produce a noise artifact known as an intermodulation spur within the ADC pass band.

Given two independent clock sources with frequencies *f*_{a} and *f*_{b}, the intermodulation products will occur at deterministic frequencies expressed by Equation 2:

where *f*_{a} and *f*_{b} can be any of the fundamental or harmonic frequencies of the clock sources, and M and N = 0, 1, 2, etc.

**Figure 2** shows how these spurs can be produced not only between the clock fundamental frequencies, but also between their harmonics.

**Figure 2 **The intermodulation artifacts produced by two fundamental frequencies, *f*_{a} and *f*_{b }include spurs from the harmonics.

Frequencies occurring close together may produce intermodulation products that appear directly in the ADC output spectrum. Other frequencies occurring further apart will produce higher-frequency intermodulation products that have the potential to alias into the ADC output spectrum, depending on the sampling rate and antialiasing filter design. If the intermodulation spurs are large enough in amplitude, they will stand above the noise floor in the frequency spectrum and degrade overall system performance for high-precision data converters.

To demonstrate the effect of intermodulation products, we captured data with a high-performance, 24-bit, delta-sigma ADC on a characterization bench board. **Figure 3** shows the frequency spectrum calculated by applying a Fast Fourier Transform (FFT) on the ADC output data.

This bench setup uses two independent clock sources: a 12-MHz clock for the DSP and an 11.997-MHz clock for the ADC. These frequencies were intentionally chosen for this example to produce intermodulation spurs at integer multiples of 3 kHz, which fall directly within the ADC’s output bandwidth. With a shared ground plane, it is not possible to electrically isolate the two clock sources.

**Figure 3 **The intermodulation spurs caused by ADC and DSP clock frequencies show up in an FFT.

**Clock source synchronization techniques**

One way to minimize the presence of intermodulation spurs in a mixed-signal design is to choose clock frequencies and switching components whose frequencies are integer multiples of one another. Unfortunately, real-world components will exhibit some amount of frequency tolerance and drift over time and temperature. These frequency variations will ultimately produce the same intermodulation effects described earlier.

Consider the following example system: with a 16-MHz ADC clock and a 64-MHz DSP clock, most of the harmonic content will occur at the same frequencies. Any intermodulation spurs formed by the ADC clock’s fundamental frequency and the first few harmonics coupling with the DSP clock fundamental will occur at frequencies of 16 MHz or greater. The ADC clock’s fourth harmonic occurs at exactly 64 MHz, the same frequency as the DSP clock. However, since these two independent clock sources are subject to minute tolerances, they will produce intermodulation spurs at much lower frequencies near DC. **Figure 4** illustrates this concept by plotting the frequency spectrum of an ADC with a DC input voltage.

**Figure 4 **Low-frequency intermodulation spurs occur near DC, an error called spectral leakage.

Figure 4 also illustrates another concept known as spectral leakage. Spectral leakage is a mathematical error that results from performing the FFT operation. In cases where the frequency spur is not an integer multiple of the FFT frequency resolution, you must use adjacent frequency bins to represent the total signal power. This is what forms the skirting effect around the low-frequency intermodulation spurs in Figure 4. Consequently, intermodulation spurs can adversely affect precision DC and low-bandwidth applications.

**Mitigating the effects of clock intermodulation and spectral leakage**

Here are some simple bench setup techniques to reduce or eliminate intermodulation spurs and spectral leakage in high-precision characterization setups.

*Anticipate spurs*

Use Figure 2 in this article as a reference to calculate where system clocks are likely to produce intermodulation spurs. If possible, adjust these clock frequencies to be integer multiples of one another, in order to minimize the potential of producing intermodulation spurs within the ADC pass band.

*Choose an input signal frequency that is closest to an integer multiple of the FFT bin size*

Remember that the bin size depends on the ADC sampling rate and the data sample size. Using windowing functions in place of a coherently sampled system will minimize spectral leakage, while retaining an accurate representation of the fundamental signal power and its harmonic content.

*Synchronize bench equipment*

All clock sources in a system should originate from one source. While this may not always be practical in a real-world application, you can achieve a synchronized characterization bench setup by using a multi-output pattern generator or an onboard clock divider circuit to generate all necessary clock signals.

You can synchronize independent pieces of equipment (clock sources, input signal source, power supplies, oscilloscopes, spectrum analyzers) by sharing a built-in 10-MHz reference clock. On the back of most laboratory instruments, you’ll usually find a reference clock input and output connection (REFIN and REFOUT, respectively). Synchronizing the input signal generator to the remaining bench equipment ensures that frequency tolerances and drift from one source are equally reflected in all other equipment on the bench, and effectively cancelled. **Figure 5** illustrates an example of how to synchronize bench equipment.

**Figure 5 **It is possible to synchronize lab equipment by using REFIN and REFOUT clock connections.

*Band-pass filter the input signal*

A high-order, passive band-pass filter is imperative for precision AC performance measurements. These filters are tuned for specific frequencies and apply high attenuation to broadband noise and harmonic content from the signal source. The resolution and distortion of the signal generator need to be much better than the characterized ADC in order to properly measure the ADC’s performance. Reducing the harmonics from the signal source also reduces the chances of producing intermodulation spurs with other AC signals on the board.

**Mixed-signal PCB design tips**

PCB design of mixed-signal systems is not trivial and requires special considerations and optimal techniques to extract the best performance from the system. For systems that cannot adhere to the four steps listed above, it may be helpful to consider a few points regarding PCB layout.

*Partially split ground planes*

The clocks for the device-under-test (DUT) and the DSP will generate transient currents on the power supplies and on the ground plane. If board space allows, place these devices and their supporting circuitry with ample separation and decoupling to discourage crosstalk. A solid ground plane is typically all that is needed in such a scenario.

However, space-constrained designs may benefit from strategically placing a partially split ground plane between major PCB sections. Limiting high-frequency current loops to only one area of the board minimizes the interaction between multiple clock signals and the production of intermodulation spurs. If necessary, you can divide the reference ground plane into three major sections: analog ground (AGND), digital ground (DGND), and DSP ground (DSP_DGND), as shown in **Figure 6**.

**Figure 6 **Splitting the ground planes in PCB layout helps mitigate clock intermodulation spurs.

At some point in the circuit, all three of the ground nets must tie together and return to the system’s original power source. Analog and digital grounds for the DUT are usually best connected directly below the device. Connecting the bench system’s main supply to the DSP_DGND side of the split should discourage any transient currents from returning through the analog side of the PCB.

*Control clock signal routing*

Keep the traces for the DUT clock and DSP clock signals short and electrically isolated from one another, as well as away from analog circuitry. If possible, surround the clock traces with the corresponding ground reference on the same PCB layer, using ground traces or a ground polygon pour. Adding a ground plane on an adjacent layer can improve clock isolation even further.

Longer PCB traces and multiple vias are prone to having more inductance, which can lead to unwanted reflections, overshoot, and ringing in clock signals. Prioritize clock signals over other digital connections between the host controller and the ADC to be as direct as possible, with minimal use of vias and other connectors. Inevitably, all clock signals will have some unwanted distortion. Use a low-pass resistor-capacitor (RC) circuit at the end of the clock trace to dampen these reflections and reduce the high-frequency harmonic energy of the clock signals. The addition of the RC circuit has the effect of slewing the clock edges enough to decrease the amplitude of their harmonics and any intermodulation tones without disrupting critical timing specifications.

*Use decoupling capacitors*

Most active components generally require local decoupling capacitors on the supply pins. It is especially important to adequately decouple the supplies for devices that generate, buffer, or accept clock signals. These active components will sink or source current from those supplies and generate small transient voltages that can interact with other devices.

Decoupling capacitors suppress these switching transients by providing a small reservoir for sudden power demands. If critical devices share the same supply as the clock circuitry, it may be best to isolate the two nets with a small ferrite bead and to add extra decoupling capacitors on each device.

**Test results validate tips in practice**

We designed a validation board following the schematic and layout recommendations outlined in this article. The board featured the Texas Instruments 24-bit, 512-kSPS ADS127L01 delta-sigma ADC and a TMS320VC5509 DSP for data collection. We measured the ADC’s performance by providing a 4-kHz sine wave from an audio precision source at the input, which we then synchronized to the rest of the bench control equipment.

As shown in **Figure 7**, the FFT spectrum plots the fundamental frequency at 4 kHz and the first three harmonics of the fundamental frequency at 8 kHz, 12 kHz, and 16 kHz. These harmonics are expected due to the minor nonlinearities associated with the input signal-chain components and the ADC itself. Aside from the fundamental and expected harmonics, there are no signs of intermodulation spurs, and the concerns with clock intermodulation are completely resolved.

**Figure 7 **A characterization setup that followed the layout and equipment recommendations in this article resulted in a clean FFT.

The techniques discussed in this article will help you improve the reliability and measurement accuracy of mixed-signal systems requiring high resolution over a wide signal bandwidth. These applications range from industrial data acquisition systems, to vibration analysis monitors, to medical instrumentation, and more. The same techniques used in these end applications also apply to ADC characterization setups to improve the repeatability of high-performance bench measurements.

*Krunal Maniar is a business development manager for precision ADCs at Texas Instruments.*

*Ryan Andrews is an applications engineer for precision ADCs at Texas Instruments.*

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