Modified clock filters improve at-speed test

Article By : Basanagouda Patil , Avinash Sekar & Peeyush Pranay

Adding programmable shift registers and separating the synchronization cell improved performance by minimizing delays and skew.

The push for higher performance at lower power and cost has driven the VLSI industry towards System-on-Chip (SoC) integration resulting in designs with multiple clocks. It is common to see blocks that share the same clock source having synchronous interactions when the frequency relation is an integral multiple of two. Often, these could be on the critical paths in the design from a timing perspective. In such situations, you must test these interactions for transition-type faults to achieve test coverage and DPPM (defective parts per million) targets.

To put it into perspective, the path, which has the launch flip-flop in one clock domain and the capture flip-flop in another synchronous clock domain, is called the Synchronous Cross-Clock Domain (SCCD) path. Figure 1 shows the combinational cloud between FF1 to FF2 is called the intra-clock domain, while the cloud between FF1 to FF3 is called the inter-clock domain.

Inter and intra clock domains in digital circuits

Figure 1. Intra- and inter-clock domain paths can introduce faults in the form of delays.

Clock Filtering Circuits (CFCs), used for transition fault testing, filter out the required clock pulses from the clock source. Typical CFCs have limitations and can’t be used for testing transition faults across these synchronous clock domains. What problems occur when you have transition faults? We will explain those limitations and propose enhancements to the CFC to make testing of SCCD, such as the inter-clock faults as shown in Fig. 1, feasible.

Figure 2 represents a typical clock filtering circuit, which has three primary components.

  • A synchronization cell to synchronize the Scan Enable (SE) signal to the operating clock domain.
  • A programmable shift register triggered by the synchronized SE signal, which controls the Integrated Clock Gating (ICG) to generate the desired number of clock pulses.
  • An ICG cell.


Figure 2: Typical Clock Filtering Circuit may not be sufficient for testing clock faults across synchronous clock domains.

At-speed fault testing involves two steps. The first step is the shift mode and the second is the capture mode. In shift mode, registers are initialized to a known value by shifting through the scan chain when the SE is high. In the capture mode, the response of the functional path is captured in the registers when the SE is low.

In capture mode, the CFC is used to generate the required clock pulses for launch and capture cycles of at-speed testing.

When SE is strobed, it arrives at the CFC after some delay. In the CFC, it is then synchronized with the two-stage synchronization cell of the receiving clock domain. The SE synchronized signal will trigger the n-stage programmable register to give an enable signal for the ICG to filter out the required clock pulses. This implies clock pulses coming out of the CFC take a certain amount of delay from the time the SE arrives at the CFC. The delay is mainly due to the synchronization cell delay.

Digital IC CFC output waveform

Figure 3. Typical CFC output waveform for at-speed testing clock.

For testing faults within a clock domain (intra-clock domain faults), this CFC works fine as shown in Figure 3. To test SCCD transition faults, however, you need to generate the launch and capture the pulses as shown in Figure 4. To achieve such waveforms, we generally use two independent CFCs. Each clock domain requires its own CFC because pulse width is different for each clock and therefore needs to be generated from a different CFC. Fig. 4 gives examples of different launch and capture condition that you can achieve.


Figure 4. Typical launch and capture pulse combination for testing inter-clock domain faults include both fast launch and slow capture, and slow launch and fast capture pulses.

When employed to test faults in synchronous inter-clock domains (Fig. 1) the same CFC encounters the following challenges:

Edge Misalignment: When testing faults between two SCCDs, each clock domain has its own CFC. This causes the outputs to be out of alignment, caused by the inherent synchronization delay attached with CFCs. The resulting clock edges will be out of the cycle alignment. For example, two synchronous clocks of frequency F and F/2, each with a programmable CFC of shift register length 4 is assumed. The programmable shift register is triggered at different times, which results in a dissimilar delay on the CFCs output. Clock domain F/2 takes twice the time as clock domain F, assuming a two-stage synchronizer. Figure 5 shows the clock output waveforms of both CFCs. It’s important to note that there are two types of misalignment. One is due to a delay in synchronization itself, which is shown in Fig. 5.

Clock filtering circuit edges

Figure 5. Clock waveform for generic CFC output, showing misaligned edges.

The other reason for misalignment is clock skew. The skew from each clock causes additional misalignment of clock outputs of the two CFCs. As shown in Figure 6, clock out of CFC_OUT_F is skewed with respect to CFC_OUT_F/2. Because of this, the functional timing window to capture the launch signal gets reduced, compromising the test quality and validity.

Figure 6. Clock skew can cause edge misalignment.

Missing Clock Pulses: Fig. 4 shows a subset of the launch and capture pulse required for at-speed testing of the inter-clock domain faults. Referring to Fig. 5, it can be deduced that for a CFC with a programmable shift register of length 4, we can’t hit all combinations of launch and capture pulses. For example, the first combination (in Fig. 4) of launch and capture pulse can be created by using the two CFCs, but not the second combination. This problem can be addressed by increasing the shift register length.

As shown in Fig. 4, to successfully test the SCCD paths, two launch and capture pulse combinations are needed. Pulses should be separated by the clock-timing window. Due to clock skew and synchronization cell delays, however, it’s difficult to achieve.

Multi-Cycle Path (MCP) Testing: Due to problems related to missing clock pulses, testing is limited by the length of the shift register. Shift register length won’t be enough to capture all the combinations of launch and capture, and this enhances more in MCP because you must wait for a cycle of one clock to pulse the other. A programmable shift register should have sufficient width to create the required MCP launch and capture the pulse and test the path. Figure 7 shows two scenarios of MCP. Again, only the first condition is possible with this CFC and not the second because it’s based on the generation of generic CFC pulses.


Figure 7. Multi-cycle paths need a shift register long enough to produce an effective launch.

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