Multi-patterning strategies for navigating the sub-5 nm frontier, part 1

Article By : Jae Uk Lee and Dr. Ryoung-han Kim, imec, David Abercrombie, Rehab Kotb Ali, and Ahmed Hamed-Fatehy, Mentor

In this first installment of a practical introduction to advanced multi-pattern semiconductor processes, we'll explore self-aligned double-patterning and self-aligned quadruple-patterning technologies.

Self-aligned multi-patterning processes have become a necessity at the most advanced nodes, where traditional litho-etch multi-patterning processes begin to experience alignment control issues, regardless of the lithography technology used. Since self-aligned processes are considerably different and more complex than traditional processes, Mentor teamed up with IMEC to provide engineers at both foundries and design houses an inside look at three production self-alignment processes—SADP, SAQP, and SALELE. With step-by-step explanations, we explain and show you the intricacies of self-aligned pattern creation needed to ensure layout fidelity in today’s most advanced nodes.

When the semiconductor industry reached the 20 nm process node, they faced a new manufacturing challenge. Extreme ultraviolet (EUV) lithography was still not production-ready, and 193i lithography being used could not accurately resolve layouts that small. The solution was the introduction of multi-patterning, a process in which layouts were split between several masks that provided enough lithographic spacing between features to enable a workable yield solution. Initially, a double-patterning (DP) litho-etch-litho-etch (LELE) process provided sufficient manufacturability. As the industry moved to smaller nodes, DP LELE was no longer adequate for some layers, and triple or quadruple patterning (TP/QP) litho-etch (LEn) processes were required to ensure manufacturability.

However, the primary concern with all LEn multi-patterning processes is alignment control. It is virtually impossible to achieve exact alignment between multiple masks at these process nodes, which makes it difficult to achieve the desired yields. The advent of EUV lithography finally offered new resolution capabilities, so many process layers that were using TP or QP with deep ultraviolet (DUV) lithography were re-engineered to use a single EUV mask, but even this process faced resolution difficulties at the smallest nodes. Given these challenges, the trend across the industry is now toward the adoption of self-aligned multi-patterning processes, in which the manufacturing process itself is used to create the required layouts.

The most common self-aligned multi-patterning technique is referred to as self-aligned double-patterning (SADP). The techniques used in SADP can also readily be extended to self-aligned quadruple-patterning (SAQP). We’ll describe how the SADP/SAQP processes work, and explain some options for the block (sometimes referred to as cut) mask needed for these processes. We’ll then introduce another process, called self-aligned LELE (SALELE), which combines aspects of both the self-aligned multi-patterning and LELE processes. IMEC and Mentor have been working jointly to create, optimize, and design-enable the SALELE process, which offers some promising advantages over the SADP/SAQP processes.

Self-aligned multi-patterning

Generally described, all of the self-aligned multi-patterning processes consist of the following steps:

  1. Print the mandrel tracks.
  2. Grow sidewalls on the sides of the printed mandrel patterns.
  3. Remove the mandrel patterns.
  4. Develop the final manufactured patterns in between the sidewalls.
  5. Add dielectric blocks to create the required tip-to-tip spacing in the final target.

Self-aligned double patterning

The basic idea behind the SADP process is essentially the same as it is for DP LELE—print every other line at double the required pitch, to accommodate lithography limitations. However, rather than printing the second set of interleaving lines using another mask, the SADP process creates them using deposition and etch processes that not only create, but also self-align these second lines, without resorting to lithography [1,2]. While there is still a second lithography operation, it is used to image a block/cut mask that defines the tip-to-tip gaps in the lines, creating the final shapes.

Let’s walk through the basic SADP process.

The first phase of any multi-patterning process is decomposition, or dividing the layout. As shown in Figure 1, the SADP decomposition process starts by converting target polygons (a) into mandrel and non-mandrel tracks (b). All target shapes must have symmetrical grating (equal spacing between tracks) and be perfectly aligned with the tracks. In the SADP manufacturing process, dummy metal is added to the desired targets to extend all target lines to the borders. After the tracks are created, the block mask (c) shapes create the required isolation between target shapes and the dummy metal (note: this non-active fill must still be extracted to measure its capacitance effect on the final design).

Figure 1 SADP decomposition: (a) input target, (b) decompose input target into mandrel and non- mandrel tracks, (c) add block mask(s).

The dielectric blocks can be printed using a single mask or multiple masks (i.e., one block mask for mandrel tracks and another one for non-mandrel tracks) to define the line ends of the active metal portions of the tracks (1c). The SADP decomposition process and the recommended procedure to get clean manufacturable layouts have been extensively discussed in industry literature [3,4].

The next phase is fabrication. As shown in Figure 2, the SADP fabrication process consists of three steps:

  • Print the mandrel tracks and transfer them to the hard mask.
  • Conformally deposit dielectric spacer over the mandrel tracks.
  • Top-down etch the dielectric spacer to open the mandrel tracks and underlayer, leaving the residual dielectric spacer as sidewalls against the mandrel shapes.
Figure 2 SADP fabrication process: (a) mandrel lines on hard mask, (b) dielectric spacer deposition, (c) dielectric spacer etched to open mandrel and underlayer. Image generated using SEMulator3D [10]

The space between the sidewalls becomes the non-mandrel tracks. Because the mandrel tracks were printed at a pitch twice the required pitch, the final correct pitch is achieved between all tracks without the need for lithography. This fabrication process relaxes the lithography process and enables foundries to print the mask with high resolution. The next step is to add the block mask shapes to create the required isolation between target shapes.

Before we get to that step, however, let’s walk through the SAQP process, and see where it is similar to, and different from, the SADP process.

Self-aligned quadruple patterning

To print even smaller pitches, SAQP is used. In this process, the mandrel core tracks are printed at quadruple pitch, and two successive sidewall operations are performed to get the final pitch. Figure 3 demonstrates the main steps of SAQP process:

  • Print mandrel core lines and transfer them to the hard mask.
  • Conformally deposit the first dielectric spacer (sidewalls) using atomic layer deposition (ALD).
  • Top-down etch dielectric spacer to remove everything except the residual dielectric spacer sidewalls around mandrel core lines.
  • Etch away the hard mask of mandrel core lines and the underlayer at the locations not covered by dielectric spacer to form the second mandrel lines.
  • Conformally deposit the second dielectric spacer using ALD.
  • Top-down etch the second dielectric spacer to open the second mandrel and the underlayer. The lines between the second dielectric spacer sidewalls create the correct pitch for the final metal lines.
Figure 3 SAQP fabrication process: (a) mandrel lines on hard mask, (b) first dielectric spacer deposition, (c) etch dielectric spacer to open mandrel and underlayer, (d) etch mandrel and transfer first spacer pattern into the underlayer, which is the second mandrel, (e) deposit second dielectric spacer around the second hard mask after removing first dielectric spacer, (f) etch dielectric spacer to open second mandrel and the underlayer. Image generated using SEMulator3D [10]

Self-aligned blocks

Now that the self-aligned tracks have been created, we can begin the task of creating the final layout with one or more block masks. The dielectric blocks (sometimes referred to as cuts, depending on the process) created with a block mask break the continuous tracks into separate pieces. The challenge of using a single block mask is that the lithography process limits the minimum spacing between block shapes, which limits the legal line-end locations. One solution is to use an LELE or LE3 process to create a block mask (or masks) that allow tighter spaces between the block shapes. However, a denser and more manufacturable solution is to use two selective block masks—one to cut the mandrel lines and another to cut the non-mandrel lines [8,9]. This selective block mask approach works by using two different materials between the sidewalls. As shown in figure 3(f), we already have the second mandrel material, and there are gaps that can be filled with yet another material. As a result, each of these materials can act as an etch stop to the other.

The self-aligned block (SAB) process, as shown in Figure 4, begins with the result of the SADP/SAQP fabrication step, and consists of the following steps:
  • Coat the wafer with the hard mask and photoresist, respectively.
  • Print the first block mask and transfer it to the hard mask. Figure 4(b) shows the pattern after removing the photoresist. A positive tone development (PTD) process with an EUV dark field mask is used in this step to generate the hole pattern. This process is selective because it only adds blocks on the non-mandrel tracks.
  • Coat the wafer with another hard mask to fill the block locations (holes).
  • Etch back the hard mask to the top of the mandrel lines.
  • Remove the hard mask (only block shapes remain).
  • Coat the wafer with the hard mask and photoresist, respectively.
  • Expose the photoresist to the second block mask.
  • Print the second block mask and transfer it to the hard mask. This time, negative tone development (NTD) is used with an EUV dark field mask to create pillars instead of holes.
  • Etch the mandrel lines at the locations not covered by the second block mask.

The pattern remaining after the photoresist and hard mask are removed represent the second block mask. Now the two masks are fully transferred to the wafer. The underlying layers are opened to form trenches that will be filled with the metal for interconnect except where there are block shapes (blue or red shapes).
Figure 4 SAB fabrication process: (a) coat wafer with hard mask and photoresist, (b) transfer pattern to hard mask, (c) coat wafer with another hard mask material, (d) etch back hard mask material, (e) strip first hard mask, (f) coat wafer with hard mask and photoresist, (g) transfer pattern to photoresist and hard mask, (h) final block pattern on the wafer. Image generated using SEMulator3D [10]

Figure 5a shows the transferred pattern in the final layer, containing the locations created by the block masks and sidewalls (the dielectric). The openings in this layer are the final metal locations (target shapes and added dummy metal). To create the interconnect metal, trenches are created at the final layer openings and filled with metal (Figure 5b).

Figure 5 (a) Transferred pattern in the final layer, (b) final manufactured shapes. Image generated using SEMulator3D [10]

Shrinking to a tighter pitch for a new node typically increases process variation, which adds constraints on block printability (block to block distance is restricted and a minimum block space rule is required). The placement of the block shapes must be optimized using different techniques, such as sliding, merging, and dropping some of block mask shapes [3,4]. However, we must still account for the additional capacitance due to the dummy metal.

Part 2 of this series introduces the SALELE process and compares the relative merits of each of the three processes covered in this series.


  1. S. Natarajan et al., “A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self- aligned double patterning and a 0.0588 µm2 SRAM cell size,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2014, pp. 3.7.1-3.7.3.
  2. Christopher Bencher, Yongmei Chen, Huixiong Dai, Warren Montgomery, Lior Huli, “22nm Half-Pitch Patterning by CVD Spacer Self Alignment Double Patterning (SADP),” Proc. SPIE 6924, Optical Microlithography XXI, 69244E (7 March 2008). 
  3. David Abercrombie, Rehab Kotb Ali, Shetha Nolke, Ahmed Hamed-Fatehy, Ahmed. “Fill/Cut SADP with Calibre Multi-Patterning,” Mentor, a Siemens Business, April, 2017.
  4. Jeanne-Tania Sucharitaves, Sam Nakagawa, Robert Yarnell, David Abercrombie, Shetha Nolke, Rehab Kotb Ali, “SADP Design Finishing : Improving results with DRC auto-fixing,” Mentor, a Siemens Business, October, 2018. 
  5. Joost Bekaert et al., “SAQP and EUV block patterning of BEOL metal layers on IMEC’s iN7,” Proc. SPIE 10143, Extreme Ultraviolet (EUV) Lithography VIII, 101430H (24 March 2017).
  6. Rehab Kotb Ali, Ahmed Hamed-Fatehy, James Word, “Integrated manufacturing flow for selective-etching SADP/SAQP,” Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 105880Q (20 March 2018). 
  7. Jongsu Lee et al., “Spacer multi-patterning control strategy with optical CD metrology on device structures,” Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97782B (8 March 2016).
  8. Angélique Raley, et al., “Self-Aligned Blocking Integration Demonstration for Critical sub 30nm pitch Mx Level Patterning with EUV self-aligned double patterning,” J. Micro/Nanolith. MEMS MOEMS 18(1) 011002 (31 July 2018).
  9. Benjamin Vincent, Joern-Holger Franke, Aurelie Juncker, Frederic Lazzarino, Gayle Murdoch, Sandip Halder, Joseph Ervin, “Self-Aligned Block and Fully Self-Aligned Via for iN5 metal 2 self-aligned quadruple patterning,” Proc. SPIE 10583, Extreme Ultraviolet (EUV) Lithography IX, 105830W (19 March 2018.
  10. Semiconductor Solutions Overview, Coventor, Inc.
Jae Uk Lee is senior R&D engineer in the computational lithography field including source mask optimization/optical proximity correction and design for manufacturability at IMEC.

Dr. Ryoung-han Kim is the director of physical design/design automation, OPC/RET, and test-site/tapeout at IMEC.

David Abercrombie is the program manager for the advanced physical verification methodology at Mentor, a Siemens business.

Rehab Kotb Ali is a senior product engineer at Mentor, a Siemens business, working on advanced physical verification technology.

Ahmed Hamed-Fatehy is a lead product engineer for RET products at Mentor, a Siemens business.

This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783247. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Netherlands, Belgium, Germany, France, Austria, United Kingdom, Israel, Switzerland.

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