Multi-patterning strategies for navigating the sub-5 nm frontier, part 3
Article By : Jae Uk Lee, Dr. Ryoung-han Kim, IMEC, and David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy, Mentor
Determine the best self-aligned multi-patterning process solution for your advanced node applications.
Self-aligned lithographic process techniques are playing an increasingly important role in advanced technology nodes. Even with the growing use of extreme ultraviolet (EUV) lithography, multi-patterning is still required for some layers at the 5-nm node and below. It is crucial to understand and consider all the process conditions, as well as other tradeoffs, when determining the best self-aligned multi-patterning (SAMP) process solution for your advanced node applications.
For dense metal layers at the 5-nm node and below, SAMP techniques have become the preferred solution. So far in this series, we described the basic process flow for three SAMP processes—the traditional approaches of self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) [Ref 1], and a new process flow called self-aligned litho-etch-litho-etch (SALELE) [Ref 2]. Now it’s time to explore and compare the advantages and disadvantages of these different SAMP techniques. In particular, we’ll discuss the flexibility for metal pitch variety between the processes, the limitations of various block mask approaches, pitch walking challenges, and differences in parasitic capacitance caused by dummy metal.
Metal width constraints
SADP
In an SADP process, the final mandrel tracks are the locations of the original printed mandrel lines [Ref 1]. This process provides full control over the width of the metal. Given that the non-mandrel tracks are defined by the gap between the spacers around the mandrel tracks, the SADP process supports any width for the mandrel and non-mandrel tracks that is within the resolution of the mandrel layer. The sidewalls’ widths (the gap between tracks) are the only constrained space, because the sidewalls are generated by an atomic layer deposition (ALD) process, which cannot vary in thickness across the wafer.
SAQP
This complete freedom of track width doesn’t exist in the SAQP process. As shown in Figure 1, the final metal pattern is a function of several process steps that interact with each other, including the lithography and etching of the mandrel core, the deposition and etching of the first sidewalls, and the deposition and etching of the second sidewalls. As a result, the final metal lines can be in the gaps between the mandrel cores (A), at the locations of the first sidewalls (B), or at the locations of the mandrel core (C). As with SADP, the sidewalls’ widths are constant per step because of the ALD process. And, because we can’t generate different sidewall widths in the same step, the width of all metal lines at B locations is constant. We can, however, vary the width of metal lines at C and A as a function of the mandrel pattern pitch.
Figure 1 Final metal width is a function of several interacting processes in SAQP.
SALELE
In SALELE, LE1 metal lines are printed directly on the wafer, and LE2 metal lines are created by printing the patterns directly aligned to LE1. LE1 metal is protected by spacers, which avoids the creation of a short between LE1 and LE2 [Ref 2]. Because both tracks are directly printed, there are no metal width or metal spacing limitations.
Design flexibility
The SAQP process always enables designs with an odd number of internal routing tracks, never an even number. As shown in Figure 1, SAQP uses two spacer depositions and anisotropic etches, so one mandrel feature creates four spacer2 layers, and one mandrel line naturally generates five metal lines with the arrangement of ABCBA. The metal located at A and C can vary in widths, but the spacer process constrains the metal width located at B.
As shown in Figure 2a, SAQP is suitable for creating an odd number of internal routing tracks with power rails on the A and C tracks. In contrast, SALELE patterning doesn’t have these design limitations, making it possible to pattern an odd or even number of internal tracks (Figure 2b). In this example, the SALELE design with four internal tracks has a cell size that is 16% smaller than the SAQP design with five internal tracks.
Figure 2 SAQP design creates an odd number of tracks (a) while SADP and SALELE design offer more flexibility (b).
In addition to track width and spacing constraints, block mask schemes are also more limited in SADP/SAQP compared to SALELE. Figure 3a shows an active metal design intent for a portion of a design. SADP/SAQP line ends are defined solely by the block mask layer(s). In this example, even with the use of dual self-aligned block (SAB) masks, two of the block mask shapes on one of the SAB masks have a minimum spacing violation (Figure 3b). Despite the availability of multiple techniques to optimize cut placement, such as cut merging, dropping, and sliding [Refs 6, 7], these techniques are not always sufficient to find a legal solution. In this example, the original design intent would have to be modified to resolve the issue. These types of constraints can potentially lead to less efficient area utilization in the routing. In contrast, for larger tip-to-tip spacing locations, SALELE can replace the block mask with direct lithographic printing, as shown in Figure 3c. This design flexibility in the SALELE process can lead to potential area reduction.
Figure 3 Comparing block mask density between SADP/SAQP and SALELE for the input design shows that SADP/SAQP decomposition (a) requires block shape at every tip-to-tip location, resulting in many potential spacing violations between block (b) and that SALELE decomposition requires block shapes only at tight tip-to-tip locations (c).
Self-aligned blocks vs. multi-color blocks
With self-aligned blocks (SABs), block masks are selectively used to block every other trench [Ref 1]. In SADP, one block mask only cuts the mandrel tracks, and the other block mask only cuts the non-mandrel tracks. In SAQP, one block mask only cuts A and C tracks, and the other one only cuts the B tracks (Figure 1). In SALELE, one block mask cuts LE1 and another block mask cuts LE2. The selective etching approach allows the block size to be extended up to the middle of the next metal track, increasing the edge placement error (EPE) budget of the block-end, and eventually the process margin of the final manufactured patterns [Refs 3, 4]. To explain this point in greater detail, let’s compare the use of multi-color block masks for SADP to the results obtained using selective-etching SABs for SADP.
Figure 4 shows the decomposition and final manufactured shapes of multi-color block masks for SADP. In Figure 4a, the original drawn target is decomposed into mandrel tracks, non-mandrel tracks, and block shapes. The block shapes are then decomposed into three block masks using triple patterning (LELELE). Non-mandrel tracks are formed between the sidewalls grown on the sides of the mandrel tracks. Each block shape is maximally extended from the two sides up to half of the gap between the tracks, seen in Figure 4b. However, we can’t extend the block shape beyond this value without notching or cutting the neighboring track, leaving a tight EPE margin for the cut shapes. This process results in the final manufactured shapes (gray) compared to the original drawn targets (black), as shown in Figure 4c.
Figure 4 Multi-color block masks in SADP help control edge placement error margins.
In contrast, Figure 5 shows a selective-etching SAB process for SADP using the same original drawn target. Figure 5a shows the target with a mandrel selective block mask that selectively cuts only mandrel tracks, and a non-mandrel selective block mask that selectively cuts only non-mandrel tracks. As shown in Figure 5b, the single cut shape can extend into half of the next track, as it selectively does not cut the neighboring tracks. This provides more margin for lithographic fidelity, a larger EPE budget for the block shapes, and eventually, a better final manufactured pattern versus the original drawn patterns shown in Figure 5c. By comparing the two final manufactured patterns generated from the two approaches, it’s clear that selective etching can provide more margin for lithographic printing than multi-color block masks.
Figure 5 Selective-etching SABs with SADP provides better error margins than multi-color masks.
When using multi-color block masks, it is necessary to create three masks for this layout, due to the spacing constraints between different masks, the spacing constraints within the same mask, and the limited EPE budget for each block shape (which prevents the block shape from getting near the neighboring track). In the selective-etching approach, two block masks are sufficient to decompose the same layout, as there are nearly no spacing constraints between the different masks. The selectivity also gives the block shapes a larger EPE budget, since a block can touch/overlap the neighboring track without affecting (cutting) it. For those who want to know even more, a detailed comparison between these two approaches from a printability point of view and lithographic fidelity can be found in Reference 5.
Pitch walking
One of the major challenges in the SAQP process is the pitch walking issue. SAQP has many process steps, including mandrel patterning, etching, deposition, etc. [Ref 1]. The effect of pitch walking can be interpreted as a critical dimension (CD) control problem in the final printed target, due to variations in the process.
Figure 6 shows how multiple process variations can contribute to a change in the final printed pattern CD. For simplicity, we assume our goal is to print target patterns of the same width and pitch; consequently, all mandrel (core) patterns are of the same width and pitch. The ideal or normal manufacturing steps of SAQP are shown in Figure 6a, where mandrel patterns are printed, and the first spacer is then grown on both sides of each mandrel pattern. The mandrel patterns are then removed, and the second spacer is grown on both sides of the first spacer patterns. The final printed patterns are developed in between the second spacer patterns, resulting in uniform CD of the final patterns. In other words, patterns A, B, and C are uniform width.
Figure 6 Process variations can induce pitch walking effects in SAQP.
In Figure 6b, process variations introduce a CD error in the printed mandrel (core) patterns, making them wider than intended. This error is propagated through the manufacturing steps, causing the final manufactured patterns to have different widths when compared to the ideal process. As the figure shows, the width of pattern A decreases, pattern B is unchanged, and the width of pattern C increases.
In Figure 6c and 6d, variation in the etching process to develop the first spacer leads to a change in the final target’s CD. The etching is considered a source of process variation, as it controls the width of the developed sidewalls. If under-etching occurs, the etching results in wider-than-ideal sidewalls. That error is propagated through the manufacturing steps and leads to a variation in the final manufactured patterns, where the width of pattern A decreases, B increases, and C remains unchanged. Conversely, if over-etching occurs, the result is narrower-than-ideal sidewalls, leading to a change in the final manufactured patterns, in which the width of pattern A increases, B decreases, and C remains unchanged.
If there is any variation in the second sidewalls, there will also be variation in the spaces between metal lines. Now imagine a combination of all these variations (mandrel core CD error, spacer deposition uniformity, first sidewalls over- or under-etching, second sidewalls over- or under-etching). The result will likely be a pattern totally different from the desired pattern. For this reason, SAQP is considered a very sensitive process, and requires very accurate process control. SALELE and SADP are less sensitive to pitch walking effects, since their CD is affected by only two factors (mandrel and spacer CD error), as opposed to SAQP’s three factors (mandrel plus spacer1 and spacer2 CD errors), as shown in Figure 7.
Figure 7 Comparison of CD determination between SAQP and SALELE/SADP shows that the latter is less sensitive to process control variations.
[Continue reading on EDN US: Parasitic capacitance and lithography]
Jae Uk Lee is a senior R&D engineer in computational lithography (including SMO, OPC, and DFM) at IMEC. His research focus is EUV lithography and advanced patterning technology. He received his M.S. and Ph.D. degrees from Hanyang University. He may be reached at Jae.uk.lee@imec.be.
Dr. Ryoung-han Kim is the director of physical design/design automation, OPC/RET, and test-site/tapeout at IMEC. His scope at IMEC covers various R&D activities across logic and memory programs in photo-lithography, OPC, mask technology, PDK/design rule/design enablement, data preparation, and DTCO. He received his Ph.D. degree in electrical engineering from Texas A&M University and his B.S./M.S. from Yonsei University, Seoul, Korea.
David Abercrombie is the program manager for advanced physical verification methodology at Mentor, a Siemens business. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions that create ever-increasing yield problems. David received a BSEE from Clemson University, and an MSEE from North Carolina State University. He may be reached at david_abercrombie@mentor.com.
Rehab Kotb Ali is a senior product engineer at Mentor, a Siemens business, working on advanced physical verification technology. She currently specializes in RET, OPC and MP/SADP/SALELE processes and products. She received a B.Sc. in electronics and communications engineering from Cairo University, and a master’s degree in Nanotechnology from American University in Cairo. Rehab can be reached at Rehab_Ali@mentor.com.
Ahmed Hamed-Fatehy is a lead product engineer for RET products at Mentor, a Siemens business. He is currently participating in the development of EDA tools that solve issues related to multi-patterning, resolution enhancement techniques, and integrated manufacturing flows. Ahmed received his B.Sc. and M. Sc. in electrical engineering from Cairo University, and is currently engaged in Ph.D. research. Ahmed can be reached at ahmed_hamedfatehy@mentor.com.
Related articles:
- Multi-patterning strategies for navigating the sub-5 nm frontier, part 1
- Multi-patterning strategies for navigating the sub-5 nm frontier, part 2
- Using AI to pattern sub-10nm ICs
- Is self-aligned double patterning cost-effective for 32 to 22 nm scaling?
- Parasitic extraction at advanced nodes
- Parasitic extraction in the age of double-patterning
