New ITAR/EAR-free space-grade FPGAs, part 2

Article By : Rajan Bedi

Many satellite and spacecraft OEMs around the world are looking for ITAR/EAR-free, rad-hard, ultra deep-submicron FPGAs. See how this new range of devices addresses that market need.

In January, I wrote an article introducing NanoXplore’s new, ITAR/EAR-free, rad-hard, space-grade FPGAs. The post described the SRAM-based fabric, the range of logic resources including the SpaceWire CODEC and embedded DSP, the basic specifications of the three devices: NG-MEDIUM, NG-LARGE and NG-ULTRA and their roadmaps, as well as sharing SEE and TID results. The new European rad-hard space-grade FPGAs address a market need for those OEMs and/or missions not wishing to design-in US export-restricted parts.
I recently received a development kit of the NG-MEDIUM FPGA and want to continue the discussion by focusing on the flow used to implement designs. NanoXmap is the Linux-based IDE that you use for synthesis, place & route, and static timing analysis via its GUI. The complete flow, from logic synthesis to generation of a bitstream, can also be controlled using the Python scripting language. NanoXpython is a wrapper that can be used to control NanoXmap, fully supporting Python syntax, structures, and external modules. NanoXmap does not contain a logic simulator so you will have to source third-party software such as ModelSim from Mentor Graphics.

I recently received an NG-MEDIUM development kit.
NanoXmap can also be downloaded as a pre-installed virtual machine for Mac OS and Windows, supporting VHDL, Verilog, and mixed-language designs. NanoXmap’s opening window has been divided into three sections: the menu (1), the design content (2), and the log console (3) as shown below.

NanoXmap GUI opening window
Once a project has been loaded, “view” displays a graphical representation of the FPGA fabric and the current design. This window is divided into five sub-sections: the progress bar (1), the command bar (2), the view window that displays the fitted design (3), a dashboard that provides an overview of the architecture (4), and a matching elements window (5) to assist user selection as illustrated below.

NanoXmap view window
The following plots show NanoXmap implementing a 32-bit encoder-decoder.

Screenshots of NanoXmap implementing an encoder-decoder
Following implementation, you can view individual nets, instances, or paths as shown below.

NanoXmap’s “select” command
Following place & route, NanoXmap generates reports listing resource utilisation including the number of LUT4s and registers. NanoXpython can also output post-synthesis, post-place, and/or post-route netlists for simulation and verification.
Following implementation, NanoXmap’s static timing analyser can generate a timing report listing the different domains, longest and shortest paths, delays, arrival times, clock skews, and setup/hold times, as well as calculating the corresponding slacks.
The complete flow, from logic synthesis to generation of a bitstream, can also be controlled using the Python scripting language as shown below.

Full FPGA implementation using Python scripting
You can download the latest version of NanoXmap, v.2.9.0, which now includes a power-estimation spreadsheet to predict pre and post-fit dissipation. Spacechips has started designing-in the NG-MEDIUM FPGAs for various clients and is bringing to market low-cost, ITAR/EAR-free on-board processors baselining the devices. We also teach and compare their performance on our FPGA training course.
My next article will demonstrate NanoXmap implementing a design on the development kit; until then, the first person to tell me how I/O pad type affects timing will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Guy from Canada, the first to answer the riddle from my previous post.
Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides on-board processing products, design consultancy in space electronics, technical-marketing, training and business-intelligence services to the global space industry. Spacechips will be teaching a three-day course on Space Electronics in Los Angeles, USA this November.
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