Pushing the maximum accurate operating frequency of the VFC beyond 1 MHz by utilizing high-speed H-CMOS logic devices as extremely fast analog switches.
Voltage to frequency converters (VFCs) are a popular method of noise-tolerant analog to digital conversion. Synchronous VFCs (like the Analog Devices AD652) in which an external, usually crystal-derived, clock provides timing for the conversion process, have significant performance advantages (speed, linearity, precision independent of passive components) over the free-running type in which conversion timing must ultimately rely on an RC time constant.
But a characteristic limitation of all VFCs, both synchronous and asynchronous, is that they make relatively slow analog-to-digital converters (ADCs) because the full-scale output frequency, and therefore conversion speed for any given conversion resolution, is limited by the analog switches used in the conversion process in which speed and precision are inherently inversely related. This design idea (Figure 1) pushes maximum accurate operating frequency beyond 1 MHz by utilizing high-speed H-CMOS logic devices as extremely fast analog switches.
Figure 1 The high speed synchronous VFC.
Here’s how it works:
D-type flip-flop #1 (FF#1) in the HC74 forms a feedback loop with op-amp #2 in the 6482 acting as a high-resolution comparator and with the high speed (~ns transition times) of the HC74 switches acting to apply 0/5V to Q1 according to the 0/1 state of the op-amp output when the FF is clocked. The duty cycle (DC1) of the FF is thus time averaged by R1C3 and servoed by the feedback loop to force VR1C3 = 5V * DC1 = Vin and DC1 = Vin / 5V. But a logic supply is typically a poor choice for a conversion reference voltage, so if this were all there was to the story, expectations for VFC accuracy would likewise be poor. We need a trick to compensate for the inevitable inaccuracy and noise in the +5V supply.
The needed compensation is provided by FF#2 implementing another feedback loop.
FF#2 is connected to form a monostable (one-shot) triggered by Fclk, applying 5V pulses to the R4C4 averaging network with pulse duration (Tp) determined by R2, R3, C1 network and op-amp #1. The voltage is averaged by VR4C4 = Fclk * 5V * Tp. Op-amp #1 compares this average to Vref and forces Tp so that Tp = Vref / Fclk / 5V. Because both FFs occupy the same chip, accuracy-affecting parameters like propagation delays, transition times, and voltage offsets will be very similar and track well over temperature and supply voltage variations, making compensation very effective.
These T duration pulses become the clock reference for FF#1, thus…
DC1 = Fout * Tp / Fclk = Fout * Vref / Fclk / 5V = Vin / 5V
…yielding (finally) the hoped-for classical synchronous VFC conversion equation…
Fout / Fclk = Vin / Vref
The resulting VFC has some useful characteristics besides high speed (for a VFC). This includes a good linearity, a tolerance of Vref in the range of 1 to 4 V, Fclk from 500 kHz to 3 MHz, operation from a single “5V+”, a 3 to 6 V supply, a low power consumption (~10 mW), very high input impedances (e.g., less than 1pA input current on Vin and Vref), and no critical or high-precision passive components.
Finally, all parts needed to build it are generic, readily available, and cheap! Total parts cost is ~$10, while by contrast the similar speed AD652, by itself, costs ~$40.
This article was originally published on EDN.