The 12.5G SerDes PHY development marks the first in a series of joint IP porting projects on UMC's 28nm High-K Metal Gate process nodes.
ASIC design service and IP provider Faraday Technology has launched its 12.5Gbps programmable SerDes PHY IP on United Microelectronics Corporation's (UMC) 28HPCU process technology. The success of Faraday's 12.5G SerDes PHY development marks the first in a series of joint IP porting projects on UMC's 28nm High-K Metal Gate process nodes and beyond.
By adopting a programmable architecture that covers data transfer rate from 1.25G to 12.5G bit per second, this SerDes IP can readily support emerging 10G/1G xPON applications, which is the “last mile” broadband access through passive optical networks. In addition, the IP supports extensive interface standards ranging from SGMII, XAUI, QSGMII, USB 3.1, PCIe 3.0, NVM Express, to SATA 3 by combining respective Physical Coding Sublayer (PCS) circuits. The versatility of the 12.5G programmable SerDes PHY significantly shortens customer's SoC design cycle time on 28HPCU.
“As the complexity of SoC integration increases along advanced process nodes, high-speed SerDes PHY technology has become the crucial building block to address a broad range of high-speed I/O interfaces in SoC applications,” said Flash Lin, Chief Operation Officer at Faraday. “28nm High-K Metal Gate technology is widely recognised to be one of foundry industry's longest node, while UMC's 28 HPCU demonstrates superior performance over industry benchmarks."