Abstract:

This paper briefly introduces the concept of power distribution network (PDN) and loop stability of voltage regulator module (VRM). Furthermore, the impact of loop stability of VRM on power integrity was studied by testing different range of phase margin and its effect on the switching noise amplitude of the VRM output. The loop stability and VRM output noise tests were performed using vector network analyzer (VNA) and oscilloscope respectively. The setup and results of analysis are discussed in detail in the later section of this paper.

Introduction:

The power distribution network (PDN) comprises all interconnects from voltage regulator module (VRM) to the integrated circuits (ICs) on the printed circuit board (PCB). A good PDN provides low noise and stable power to ICs. The major parts of PDN are VRM, bulk bypass and decoupling capacitors, plane, die capacitance and vias [1]. A typical PDN topology is shown in Fig. 1 [1]. In this paper, the impact of VRM loop stability (i.e., phase margin) on the power integrity (i.e., VRM output switching noise amplitude) was studied.

TEDC2 figure 1

Fig. 1. PDN topology

A switch mode VRM depends on a closed feedback control loop to make sure that the expected output voltage and current are well maintained under different load conditions [2]. The major performance aspects of the VRM such as line/load regulation, stability and dynamic response are affected by tuning the control loop [2]. A typical VRM control loop is shown in Fig. 2 [3]. The feedback control loop is optimized by tuning the compensation network hardwired to the VRM [2].

TEDC2 figure 2

Fig. 2. Typical VRM control loop

The control loop is characterized by its frequency response that indicates how a VRM reacts under the defined operating conditions across certain frequency range. The frequency response of the VRM shows how variations in the input voltage, load and duty cycle affect the output voltage in frequency domain. The VRM’s reaction time, precision and stability are affected by its frequency response [2].

With reference to Fig. 2, negative feedback from output back to an error amplifier is applied by VRM to guarantee proper regulation over different operating conditions (e.g., varying load, input voltage and temperature). The measurement and plot of gain and phase for a complete path around the closed loop are performed to ensure stability in a feedback circuit [3]. Phase and gain margin are used to determine feedback loop stability. An improper feedback loop design results in VRM output instability such as oscillation, overshoot, undershoot, and other unexpected characteristics that lead to system malfunction [3]. The Bode plot in Fig. 3 [3] is an example showing the VRM loop gain and phase. For step down VRM with negative feedback, phase margin is the measurement between phase plot and 0o at crossover frequency (i.e., frequency where control loop input-to-output gain crosses 0dB).

TEDC2 figure 3

Fig. 3. Example of Bode plot showing VRM loop gain and phase

With reference to Eqn. (1) [4], the crossover frequency is selected equal to one tenth to one fifth of the VRM switching frequency to achieve a stable loop. Furthermore, minimum 45o phase margin is used as a safe target specification. Lower phase margin results in a faster loop response time but risks the possibility of instability in the control loop [3]. Fc = (1/10 ~ 1/5) x Fsw (1) Fc = crossover frequency of the loop Fsw = switching frequency of the VRM

Analysis and Results:

In order to study the impact of loop stability (i.e., phase margin) on power integrity (i.e., VRM output switching noise), the compensation filter that consists of a resistor and capacitor (RC) series network in a VRM under test was tuned to achieve various phase margin (i.e., 66.43o, 20.87o, 0.38o and -22.26o) and subsequently VRM output noise amplitude was observed.

The loop gain and phase measurement was performed using Keysight’s vector network analyzer (VNA) E5061B, with test setup illustrated in Fig. 4 [5]. In this test, the VRM steps down 5V to 1.2V with load condition 1A. The VRM has 520kHz switching frequency. The low impedance test signal of VNA (i.e., power set as -30dBm, sweeping from 100Hz to 1MHz) was injected across the 50 ohm shunt resistor (i.e., inserted between output and feedback network of VRM) via an isolation transformer to measure the loop gain with the ratio measurement T/R without disturbing the original loop characteristics of the VRM under test [5] and also to avoid the power being injected back to the VNA that potentially causing damage to the instrument [3]. At the same time, passive probes were connected across the shunt resistor while port T and R of VNA were set with 1Mohm input impedance. All the wiring in test setup shall be kept as short as possible to minimize the parasitic that might affect measurement accuracy.

TEDC2 figure 4

Fig. 4. Test setup for loop gain and phase measurement using VNA E5061B

<p>Subsequently with the same aforementioned input and load condition, the VRM output in time domain for various phase margin (i.e., 66.43o, 20.87o, 0.38o and -22.26o) by tuning compensation RC network was measured using Keysight’s oscilloscope MSO6102A (i.e., input channel set as DC coupling and 1Mohm impedance). The Bode plots in VNA E5061B and VRM output waveform plots in oscilloscope MSO6102A for various test cases are shown in Fig. 5-8. </p>
<p>With reference to results of test case 1 in Fig. 5, where compensation RC network was tuned to achieve 66.43o phase margin and ~ 57kHz crossover frequency, the VRM output waveform ramped up nicely without overshoot and undershoot. The switching noise amplitude was 25mVpp (i.e., ±1% of 1.2Vout) at steady state. Assuming this Vout is supplied to the core of FPGA, which requires 1.2V ±5% under normal operating condition [6], this compensation RC network design meets the specification.</p>

TEDC2 figure 5

Fig. 5. Bode plot (left) and output waveform (right) of VRM at 66.43o phase margin

On the other hand, according to results of test case 2 in Fig. 6, where compensation RC network was tuned to achieve 20.87o phase margin and ~ 38kHz crossover frequency, the VRM output waveform ramped up with 1.28V overshoot. The switching noise amplitude was 50mVpp (i.e., ±2% of 1.2Vout) at steady state. Assuming this Vout is supplied to the core of FPGA, which requires 1.2V ±5% under normal operating condition [6], this compensation RC network design does not meet the specification as the ramp up overshoot of 1.28V that is over the maximum limit stated in the recommended operating condition in [6], would cause long term reliability problem to the electronic load.

TEDC2 figure 6

Fig. 6. Bode plot (left) and output waveform (right) of VRM at 20.87o phase margin

<p>Meanwhile, based on results of test case 3 in Fig. 7, where compensation RC network was tuned to achieve 0.38o phase margin and ~ 36kHz crossover frequency, the VRM output waveform ramped up with 1.6V overshoot. The switching noise amplitude was 70mVpp. Assuming this Vout is supplied to the core of FPGA, which requires 1.2V ±5% under normal operating condition [6], this compensation RC network design does not meet the specification as the ramp up overshoot of 1.6V that is over the maximum limit stated in the recommended operating condition in [6], would fail the system boot up and cause long term reliability problem to the electronic load.</p>

TEDC2 figure 7

Fig. 7. Bode plot (left) and output waveform (right) of VRM at 0.38o phase margin

<p>Referring to results of test case 4 in Fig. 8, where compensation RC network was tuned to achieve -22.26o phase margin and ~ 78kHz crossover frequency, the VRM output waveform had switching noise amplitude 160mVpp. Moreover, the switching frequency was 55kHz, instead of the 520kHz observed in the previous three test cases. This compensation RC network design caused the switching malfunction and output oscillation much larger than the load tolerance under normal operating condition stated in [6]. This would fail the system boot up and cause long term reliability problem to the electronic load.</p>

TEDC2 figure 7

Fig. 8. Bode plot (left) and output waveform (right) of VRM at -22.26o phase margin

Conclusion:

Power integrity is an aspect of how stable and low noise the power is supplied to the electronic loads via PDN on PCB. The investigation effort in this paper proved that VRM loop stability (i.e., phase margin) affects the power integrity (i.e., output switching noise characteristic). For minimum VRM output overshoot, undershoot and oscillation, it is recommended that the compensation network be tuned to achieve minimum 45o loop phase margin and crossover frequency between one tenth and one fifth of the VRM switching frequency under the specified input supply and output load condition.

References:

  • [1] B. Olney, Power Distribution Network Planning, http://www.icd.com.au/articles/PDN_Planning_PCB-May2012.pdf
  • [2] S. Keeping, Understanding Switching Regulator Control Loop Response, https://www.digikey.com/en/articles/techzone/2015/sep/understanding-switching-regulator-control-loop-response
  • [3] R. Hanrahan, Testing a Power Supply – Stability, http://www.edn.com/design/power-management/4412230/Testing-a-power-supply---Stability--Part-3-
  • [4] M. Rahimi, P. Parto and P. Asadi, Compensator Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier, https://www.infineon.com/dgdl/an-1162.pdf?fileId=5546d462533600a40153559a8e17111a
  • [5] Keysight Technologies: Evaluating DC-DC Converters and PDN with the E5061B LF-RF Network Analyzer, http://literature.cdn.keysight.com/litweb/pdf/5990-5902EN.pdf
  • [6] Xilinx Spartan-6 FPGA Data Sheet: DC and Switching Characteristics, https://www.xilinx.com/support/documentation/data_sheets/ds162.pdf