When building 5G wireless receivers, SAR ADCs can be coupled with capacitive DACs to stabilize the reference voltage, a key technique that helps the receivers achieve desired throughputs.
Coupling SAR ADCs with capacitive DACs is a popular approach to realize energy-efficient conversion for the medium resolutions and speeds that are required for 5G wireless receivers. In combination with techniques like pipelining, interleaving, and digital calibration, hybrid ADCs with accuracies up to 12-bit ENOB (effective number of bits) and speeds of several hundred MHz have been demonstrated. With these properties, these ADCs can provide the throughputs required for 5G applications.
While the ADC itself is very power-efficient, it also poses tough constraints on the circuitry surrounding it, especially when it comes to the reference voltage. Indeed, the DAC draws a signal-dependent charge from the reference – a common characteristic for all successive approximation register (SAR) ADCs that implement capacitive DACs. Without measures to stabilize this reference voltage, signal-dependent modulation of the reference voltage results, which shows up as harmonic distortion at the ADC output.
Conventional solutions include adding more on-chip decoupling capacitance or high-speed reference buffers at the cost of area and/or power.
The signal-dependent charge drawn from the reference is fully determined by the specific DAC topology. Hence, it is predictable and the reference can be stabilized by cancelling the signal-dependent charge with another signal-dependent charge that eliminates the ripple on the reference voltage. Imec has now successfully implemented such a reference stabilization technique based on the use of auxiliary DACs in its interleaved pipelined SAR ADC.
Figure 1 shows the basic concept of this stabilization technique. When the input signal is sampled onto the main DAC, the reference voltage is also sampled onto a reference capacitor Cref, while an auxiliary DAC Caux is discharged (step 1). When the main DAC then switches to generate the residue according to a code B1, a code-dependent number of units of the auxiliary DAC is also connected to the reference node (step 2). By choosing the appropriate size of Caux per code B1, the sum of the charges drawn by the main DAC and the auxiliary DAC can be made constant. The reference voltage drops but the drop is now signal-independent.
Finally, the main DAC resets to its original state. This operation also draws a signal-dependent charge from the reference. By using the same stabilization technique with a second auxiliary DAC Creset, this second reference voltage drop also becomes signal-independent (step 3). The reference buffer now only needs to recharge Cref with a constant amount of charge which greatly relaxes its bandwidth requirement.
Figure 2 depicts the diagram of the 2× interleaved pipelined SAR ADC which implements the stabilization technique discussed above. In this architecture, the most critical residue is the final one generated by the first stage. Hence, the stabilization technique is only applied when this residue is generated by the main DAC. This DAC uses 2 sub-DACs for the positive and negative input ranges which reduces the switching energy but also results in a very nonlinear mapping of the code B1 onto the right settings for the auxiliary DAC Caux needed to cancel the signal-dependency of the charge drawn by the main DAC.
The 6-bit code B1 is determined by small coarse SAR quantizer, which only needs 6-bit linearity so no stringent conditions on its reference are imposed. A look-up table (LUT) maps the code B1 onto the right setting for the auxiliary DAC. Then, the main DAC switches together with connecting the auxiliary DAC Caux to the reference node. After the amplification of the residue, the main DAC resets and the auxiliary DAC Creset is connected to the reference node as explained above. The amplified residue is further quantized by the second stage to achieve an overall 14-bit quantization level.
The LUT is addressed concurrently with the coarse SAR quantizer to greatly reduce the critical timing path. To fill the LUT, a comparator with built-in offset compares the final reference voltage with the nominal value Vref0, and a calibration engine adjusts the Caux setting per code B1. The settings for Creset are well approximated by a piecewise-linear decoder.
Figure 3 Chip micrograph
A test chip has been fabricated in 16nm FinFET technology. The core area is 350×325 μm2 with 16 percent of it used for the reference stabilization scheme including Cref of 50pF. The measured reduction of harmonics with the capacitive stabilization technique is shown in Figure 4. For high-speed operation, both Caux and Creset improve the SFDR (spurious-free dynamic range) significantly and the spurs are suppressed to below 80 dBFS. At 303 MS/s, the SNDR (signal-to-noise plus distortion rate) is 64.0 dB and 69.3 dB with low-frequency and Nyquist inputs, respectively. Power is only 3.6 mW, resulting in state-of-the-art Walden and Schreier FoMs of 9.2 fJ/conv.-step and 170.2 dB, respectively, as shown in Figure 5.
Figure 4 Reduction of spurs with auxiliary DACs
Figure 5 Comparison of ADC with different state-of-the-art architectures
These results demonstrate that the reference voltage can be stabilized by using auxiliary DACs that remove the signal-dependent drop of the reference voltage due to DAC switching in a SAR ADC. When also applied when the DAC resets, the load on the reference node is made signal-independent which reduces the requirements on reference buffers and/or on-chip decoupling capacitance significantly.