Many satellite and spacecraft OEMs are looking for ITAR/EAR-free, rad-hard, ultra deep-submicron FPGAs. BRAVE, a new family of rad-hard FPGAs, addresses this market need.
Firstly, Happy New Year to all readers of Out-of-this-World Design. I have many interesting articles on space electronics planned for 2018 which I hope you will find interesting and helpful.
Last September, I attended the first BRAVE FPGA Day held at ESTEC to share early experiences and the formal launch of a new family of European, rad-hard, space-grade, SRAM-based FPGAs being developed by a French company called NanoXplore.
BRAVE stands for “big re-programmable array for versatile environments” and is a European initiative supported by ESA, CNES, and NanoXplore to develop a range of International Traffic of Arms Regulations (ITAR) and Export Administration Regulations (EAR)-free, rad-hard, SRAM-based FPGAs.
Three rad-hard device families are planned: NG-MEDIUM, NG-LARGE, and NG-ULTRA, with increasing fabric size and number of logic resources. A combination of radiation hardening by process, layout, architecture (EDAC), and circuit design (TMR flip-flops and DMR clock-tree), together with a background scrubber to preserve the integrity of the internal configuration, are used to provide a rad-hard fabric.
The BRAVE devices are based on a LUT4-based fabric comprising programmable logic, embedded RAM, DSP blocks, and peripheral I/O buffers. The micro-architecture is interleaved with interconnect structures to provide routing within the fabric and to the I/O banks. The programmable logic resources are arranged in a hierarchical structure called a TILE, with each containing 408 LUT4s, 384 D-type flip-flops, two register files, carry logic, and LUT extension capability.
Figure 1 Fabric of BRAVE NG-MEDIUM FPGA
NanoXplore presented NG-MEDIUM's radiation test results at the first BRAVE FPGA Day, including heavy-ion, SEE cross-section curves for the configuration, flip-flops, clock, EDAC, and scrubber circuits. The resulting GEO upset rate based on a solar minimum and 100 mils of aluminium shielding calculated using a Weibull fit is specified to be 1.7E-4 errors per device day, equivalent to one error every 16 years. Total-dose tolerance is listed as 100krads (Si) but devices were tested up to 300 krads (Si). Latch-up is specified as 60 MeV at 125°C and elevated core voltage. Proton testing was also carried out last quarter with good results and a formal test report will be published shortly.
NG-MEDIUM parts have been fabricated using STMicroelectronics' rad-hard 65 nm process and two devices are currently available: a 625-pin, 29×29 mm LGA, and a 352-pin, 48×48 mm MQFP. Both contain 35k LUTs, 2.8 Mb of embedded RAM, one 430 Mbps SpaceWire CODEC and embedded DSP, and are available today with ESCC and QML qualification expected in Q2 and Q3 of this year respectively. The 625-pin device offers 12 I/O banks while the 352-pin version contains eight.
Figure 2 NG-MEDIUM development kit
NG-LARGE will also be fabricated using STMicroelectronics' rad-hard 65 nm process and will contain 140k LUTs, 10.1 Mb of embedded RAM, packaged in a 1752-pin LGA/CGA with first parts available in Q3 of this year. NG-LARGE will also offer 24, 6.25 Gbps high-speed serial links, one 400 Mbps SpaceWire interface, embedded DSP, a rad-hard ARM Cortex-R5x core, and 24 I/O banks.
NG-ULTRA will be fabricated using a 28 nm FD-SOI process, will contain 600k LUTs, 32 Mb of embedded RAM, packaged in a 1752-pin LGA/CGA, with first parts available towards the end of 2019. The target logic and DSP performance is 500 and 800 MHz respectively, 1 Gbps differential I/O, 12.5 Gbps SERDES links and a 600 MHz quad-core ARM R52.
A Linux, Python-based IDE, known as NanoXmap, is used to implement designs on the BRAVE devices and screen shots are shown below:
Figure 3 Screen shots of NanoXmap IDE
The BRAVE family of ITAR/EAR-free, rad-hard FPGAs addresses a real export need and Spacechips has started designing-in the BRAVE FPGAs for various clients and is also bringing to market a low-cost, ITAR/EAR-free on-board processor baselining the BRAVE devices.
To meet your time-to-market needs and reduce hardware development costs, a scalable power-distribution architecture for the BRAVE parts has been created, which allows you to select different regulators (COTS for space or fully qualified) based on the choice of BRAVE FPGA. Similarly, various configuration memory options can also be chosen. These concepts exploit the Design Reuse feature provided by the Mentor Graphics' xDxDesigner/Expedition PCB flow, which allows certified schematic and layout blocks to be imported into different projects.
To increase productivity, Mentor Graphics' xDxDesigner/Expedition PCB flow also provides a Variant Manager to allow you to quickly select the desired manufacturing build, e.g. test components used by BRAVE devices during prototyping can be removed from the flight hardware with the software automatically generating the appropriate schematic, BOM, and assembly drawing. If you would like to learn more about designing-in the BRAVE FPGAs, I compare BRAVE devices with all other space-grade PLDs (and some COTS) in my FPGA course. Powering and clocking BRAVE devices are also discussed.
Later this year, I plan to publish further articles on BRAVE FPGAs and also present a webinar to discuss and compare their performance implementing spacecraft IP. The first person to tell me how a hardened, 12-transistor SRAM cell provides better SEU tolerance than a conventional six-transistor design will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Fernando from Spain, the first to answer the riddle from my previous post.
P.S. Thank you for your many messages, good wishes, and continued support. We are so pleased that Spacechips won New Company of the Year and High-Reliability Product of 2017.
Rajan Bedi is CEO of Spacechips Ltd, which provides industrial R&D and space electronics design consultancy services to manufacturers of satellites and spacecraft around the world.