The longer it takes to detect errors in an IC design, the more expensive those errors can be. Moving from a UVM testbench to an emulator can accelerate and improve test coverage.
While IC design complexity increases, the amount of time allotted for designing ICs remains about the same. That compels engineers to accelerate all the processes involved. I’m a member of a team that recently ported to an emulation environment to make the test process faster and more effective. We’d like to share some of what we learned.
Spending too much time on testing risks missing marketing windows of opportunity. Spending too little risks missing design errors. Failing to discover an error until the mask stage can be exceedingly expensive. The minimum cost of creating a mask at 7 nanometers (nm) is now about $10 million – and that’s for a relatively small IC.
As we move to more intricate SoC designs, using test time effectively becomes increasingly crucial. With several avenues to test our design, we have to pick and choose the best ways to optimize the testing and time spent. Emulation stands out as a way to improve your testing time, though the way is not straightforward.
It led us to make several changes in our testbench setup and in our design process, including some changes in our SVAs (SystemVerilog assertions). We also identified which kinds of tests and which level of testbenches running tests on emulation would give a very high return on investment (ROI).
We start with an overview and then boil down to some code samples. We offer things to look out for, and suggest how to plan effectively. We’ll come up with an improved Virtual Interface (Vif++) to help us in our porting process. In the industry standard verification methodology, UVM, a virtual interface (Vif) is a shared piece of code between components in an interface.
Here the term emulator is used interchangeably with any simulator capable of executing RTL or gate-level models, including software HDL simulators. The potential for speeding the process is the most for hardware-based ones, so that’ll be our focus.
To verify complex designs, we now have several tools and techniques at our disposal, including simulators, emulators, SVAs, functional coverage, and formal verification. All of them work on different levels to bring us closer to the ultimate goal of getting bug-free design as fast as possible. Emulators help us to speed up our runtime to the order of 100-1,000,000× and more.
In Figure 1 we see what the current state of time consumed to simulate is to the goal we are shooting for. Following are techniques to reach Level 3 performance.
[Continue reading on EDN US: Co-emulation: best tests]
Jigar Savla is an ASIC design and verification engineer at Juniper Networks.
- Hardware-assisted verification, from its dawn to SystemVerilog, UVM, and transactors
- A standard who's time must come – SCE-MI
- Experiences with hardware emulation
- Moving to virtual emulation for software-defined networking
- A short course on SystemVerilog classes for UVM verification
- Improving analog design verification using UVM
- Get a handle on design languages