In board designs, power integrity and signal integrity are very important factors and power delivery network (PDN) design plays a vital role in analyzing these factors. In the beginning of board designs, PDN performances were not considered as major criteria. In today’s scenario with development in semiconductor technologies, for devices with lower voltage, higher current, and low voltage noise margin, PDN performances should be optimized to meet the device specifications.

This article explains the PDN, target impedance range, and discusses the components required to keep the target impedance in its range. It also discusses the challenges and effects of the PDN components including the voltage regulator module, bulk decoupling capacitors, and power plane parasitics. A case study also presents a debugging approach for resolving noise issues in the PDN in the absence of bulk and decoupling capacitors.

PDN design is getting more complex and difficult with advancements in semiconductor technologies. There are several types of semiconductor products for which power distribution is very necessary to run them properly. Nowadays, electronic boards are getting densely packed and the number of on board voltages are increasing rapidly. So, it is essential to board designers to deliver the right power to all the on-board devices with optimum space and highest efficiency. Also, as clock frequency rises, and more and more functions get integrated into a single SoC, power consumption increases. Along with that, strict noise requirements are also increased for proper functioning of the device, which creates various challenges towards the design of a PDN, i.e. power quality also limits the performance of circuits and has become a determining factor in how reliably they work.

Here, the reactive part of the system is comprised of chip capacitance, package inductance, and structures of the PCB. This reactive part of the system, often referred to as system reactance, usually gets ignored by designers, and always dominates IR drop. Resonant structures get formed due to system reactance which stores and releases energy in different frequency bands. The whole of the system should be contemplated in order to estimate the impedance peaks in the frequency domain and overshoots and undershoots in the time domain. The system should be analyzed as a whole because estimation of resonances is not possible by only analyzing the board, chip, and package individually. [4]

Methods to distribute voltage and power to all the active devices requiring power and to keep the noise below an acceptable level, are discussed below, followed by a case study that discusses the scenarios which can arise in the absence of bulk and decoupling capacitors and how to debug those scenarios.

Power delivery network
The ultimate purpose of a PDN is to supply noiseless power to the devices on the PCB. It consists of all the interconnects in the path from the voltage source to the circuits on the PCB. Figure 1 shows a very simple depiction of a PDN.

ZPDN is an impedance of the path between VRM and the load. The measure of voltage ripple, which can be seen on a given power rail, is comparable to the transient current (ITRANSIENT) incorporated with that rail and the impedance (ZPDN). [3]

Based on Ohms law:
VRIPPLE= ITRANSIENT*ZPDN

So VRIPPLE is proportional to transient current and impedance. But transient current is totally specific to the application and can only be determined during the run time. Board designers have no control of this parameter. So, the only way left for designers to minimize voltage ripple is reducing ZPDN, as this is under the control of designer. To design a system which is having noise voltage ripple within the desired limit, the PCB must be designed in such a way that ZPDN meets a certain impedance, that is called ZTARGET.

Figure 1 System PDN [3]

Target impedance (ZTARGET)
The first step towards any PDN design is to identify the target impedance for a wide frequency range. This is essential as the current transients can exist at different frequencies, which makes it a necessary requirement that target impedance be established for all frequencies and not just at DC.  The target impedance is defined as:


where,
Max Transient Current = maximum change in current over a defined frequency range; %Ripple = maximum expected ripple (noise) on a voltage rail.

In order to classify design guidelines for any PDN, a target impedance is identified that is low enough to deliver power with optimum quality and at minimum cost i.e. an efficient PDN design minimizes the impedance such that ZPDN either meets or is lower than ZTARGET. It is called target impedance because if the actual impedance is greater than target impedance then then probability of circuit malfunction will be very high, whereas if the actual impedance is less than target impedance, it unnecessarily increases the cost. From a design standpoint, certain trade-offs must be made to achieve balance between cost and performance of the circuits depending on the target impedance. Apart from that, it may or may not be possible under all scenarios to design a PDN with ZPDN under ZTARGET. [3][4]

PDN and its components
A PDN requires various components to establish ZTARGET over a wide frequency range. It can either be very simple or extremely complex depending on its design. A simple PDN design can be classified as one which receives its power through some edge connector which is connected to an external power source, i.e. from a source which is not present on the board. From the edge connector the power can be distributed to the devices through appropriately routed traces. Similarly, a complex PDN design can be classified as one which has one or more voltage regulator modules (VRM’s), some components or circuits to improve power quality such as a decoupling capacitor, bulk capacitor or multistage LC filters, and a closely spaced system of ground and power planes to distribute power along the board such that the planar capacitance is uniformly distributed [2]. A complex PDN design can be seen in Figure 2.

Figure 2 A PDN consisting of VRM, bulk and decoupling capacitor, and power and ground planes [1]


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