Electronically-variable capacitors, whether used for T&M or in an end circuit, usually have a maximum capacitance of a few hundred picofarads, and a limited adjustment range. This Design Idea demonstrates a wide-range, variable, high-valued capacitor.

Figure 1  The circuit in the dashed box illustrates the variable capacitor topology.

Here are the relevant equations:

Figure 2 Practical implementation of the variable capacitor. The Verr blocks are discussed later.

I used the OPA189 due to its very low offset voltage, and the OPA633 due to its high output current.

With the values shown in the schematic:

ki = 1

kd = C1 × (P1+R7)

Changing the value of the potentiometer we get a capacitance of 100 nF to 4.8 µF.

Figure 3 Simulation results for P1 = 3.2 kΩ.

Figure 4 Actual waveforms of Ic and Vc.

As a further test, I connected a 2.2 mH coil between Vc and ground. The circuit rings at 1.87 kHz, which agrees well with the expectation.

Figure 5 Ringing (1.87 kHz) of 2.2 mH and 3.3 µF.

Influence of op-amp common-mode rejection
Considering the error sources at the outputs of U1 and U3 due to the mismatches in R3-R6 and R8-R11, we get:

We can neglect the second term due to very high value of denominator.

But, the error due to the CMRR of U1 cannot be neglected. The differential input voltage of U1 is very small (Vc – Vo), while the common input voltage is high, namely Vc .

The CMRR due to resistor mismatch is: 

  where Gd is the differential gain.

Using 0.1% resistors for R3-R6, the CMRR will be 54 dB.

Download TINA simulation files.

Gheorghe Plasoianu has a Masters degree in electrical engineering from the Polytechnics Institute of Bucharest.


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