I. INTRODUCTION

The power distribution network (PDN) is a system that transfers low noise and stable power to the loads (e.g. ICs) on printed circuit board (PCB). It also provides a low impedance return path for signal's current flow. The four major elements of PDN include voltage regulator module (VRM), bypass or decoupling capacitors, power plane capacitance and interconnection inductance.

A typical PDN topology that lumps all the four major elements and other parasitic is shown in Figure 1 [1]. Resonant frequency profile of each PDN element is illustrated in Figure 2 [1], which is represented by Equation (1) [1], where the frequency is inversely proportional to square root of inductance and capacitance. All these PDN elements lump together and form the PDN impedance.

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Fig. 1. PDN topology (B. Olney, 2012)

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Fig. 2. Resonant frequency of PDN elements (B. Olney, 2012)

(1)

f = resonant frequency L = parasitic inductance C = capacitance

When VRM supplies power to the load, the transient current at the load interacts with the PDN impedance and generates noise ripple that flows back to the PDN. In order to minimize the noise ripple, PDN impedance shall be kept below the targeted impedance, which is governed by Equation (2) [2]. Best practices to design PDN with low impedance are discussed in subsequent section of this article.

(2)

Vripplemax = maximum ripple at power rail Imax = maximum current loaded by ICs

II. PDN DESIGN WITH LOW IMPEDANCE

In order to design a PDN with low impedance, elements such as bypass or decoupling capacitors, power plane capacitance and interconnection inductance must be monitored closely.

With reference to Figure 2, bypass capacitors help keep the PDN impedance low at frequency range between hundreds of kHz and hundreds of MHz. A capacitor's behavior is non-ideal, which is represented by lumped circuit model shown in Figure 3, where the actual capacitance is in series with parasitic inductance (ESL) and resistance (ESR) [3]. Observing impedance profile of the capacitor in Figure 4 [2], the impedance can be reduced by decreasing the ESL and ESR. Ceramic capacitors with material COG, X7R or X5R have very low ESR. Meanwhile, a lower parasitic inductance can be achieved by using capacitors with smaller package dimension [2].

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Fig. 3. Circuit model of a bypass capacitor

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Fig. 4. Relation between impedance and C, L and ESR (F. Carrio, 2011)

On the other hand, different active load ICs have different requirements for bypass capacitors. A table that summarizes the required quantity of bypass capacitors for different power rails of Xilinx's Spartan-6 FPGA is shown in Figure 5a [4]. For example, device LX4 with package TQG144 requires the placement of two 4.7 uF and one 0.47 uF bypass capacitors at VCCINT rail. To maximize the effect of noise suppression for the power rail, bulk bypass capacitors (i.e., capacitance larger than 1 uF) shall be placed as close as possible to the output of the VRM to filter low frequency noise, while decoupling capacitors (i.e., capacitance in sub-uF range) shall be placed as close as possible to the load to filter high frequency noise. The simulated plots of PDN impedance depicted in Figure 5b indicates that when 3 bulk bypass and 8 decoupling capacitors are placed along the power rail, the PDN impedance (i.e. green curve) of the PCB stays below 0.2 ohm across the wideband. Meanwhile, the PDN impedance soars above 0.5 ohm below the frequency of 1.5MHz (i.e. red curve) and beyond the frequency of 200MHz (i.e. blue curve) due to the removal of bulk bypass capacitors and decoupling capacitors respectively.

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Fig. 5a. Required quantity of bypass or decoupling capacitors for Spartan-6 FPGA (Xilinx, 2012)

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Fig. 5b. Simulated PDN impedance plots for various decoupling conditions

The PDN impedance can also be minimized by increasing the power planar capacitance. Referring to the simplified model of plane capacitance illustrated in Figure 6a and Equation (3), capacitance is increased by enlarging the area of parallel planes between power and its reference plane, decreasing the substrate thickness between the parallel planes and using substrate with higher dielectric constant. A simulation is performed to compare the PDN impedance for a dummy power plane with embedded capacitance material or ECM (i.e., εr of 9.5 and d of 0.5 mil) versus FR4 (i.e., εr of 4.3 and d of 6.5 mil). The overlapped area between the power and ground plane is 4 inches by 3 inches. The simulated plot is depicted in Figure 6b, where PDN impedance with ECM is reduced as much as 0.1 ohm from 100 MHz up to 500 MHz versus FR4.

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Fig. 6a. Model of planar capacitance

(3)

εr = dielectric constant of substrate εo = permittivity of vacuum w = copper width l = copper length d = substrate thickness

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Fig. 6b. Simulated PDN impedance for power plane with FR4 versus ECM

Another key step is to minimize the interconnection or loop inductance, illustrated in Figure 7a [2]. The loop inductance is mainly contributed by the parasitic inductance of the via and the trace connecting the capacitor's mounting pad and the via. Parasitic inductance due to via is represented by cross section image in Figure 7b and Equation (4) [5]. Meanwhile, strip inductance of the trace between mounting pad and via is represented by Equation (5) [6].

The simulated impedance plots for a 0.1 uF capacitor in shunt configuration depicted in Fig. 8a indicates that across the wideband, without interconnect trace at all (i.e., pink curve), the impedance of capacitor experiences the lowest impedance. At 500 MHz, a further increase of interconnect trace length to 10 mil (i.e., black curve) worsens the impedance by 0.5 ohm. Meanwhile, the simulated impedance plots for a 0.1 uF capacitor in shunt configuration depicted in Fig. 8b indicates that across the wideband, with 3 mils interconnect via height (i.e., green curve), the impedance of capacitor experiences the lowest impedance. At 500 MHz, a further increase of interconnect via height to 8 mil (i.e., blue curve) worsens the impedance by 1 ohm. Hence, to minimize the interconnection inductance, via height shall be reduced by decreasing the substrate thickness between the power and its reference planes. The via-in-pad shall also be applied to nullify the effect of strip inductance.

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Fig. 7a. Interconnection or loop inductance (F. Carrio, 2011)

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Fig. 7b. Structure of via (Texas Instruments, 2012)

(4)

L = parasitic inductance of via h = via height d = via hole diameter

(5)

L = strip inductance l = trace length w = trace width t = trace thickness

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Fig. 8a. Simulated impedance plots for capacitor with varying interconnect trace lengt)

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Fig. 8b. Simulated impedance plots for capacitor with varying interconnect via height

III. SIMULATION OF PDN IMPEDANCE

Once the PCB is laid out, post-layout power integrity simulation is done to compute the PDN impedance profile using Mentor Graphic Hyperlynx. Proper configuration shall be performed in Hyperlynx prior to the simulation for higher accuracy.

After the PCB layout is imported to Hyperlynx, complete stack-up info must be keyed in. Subsequently, simulation models of the bypass capacitors (i.e., SPICE or Touchstone) are imported to the CAD tool. These behavioral models are available on the capacitor manufacturers' websites.

This is followed by starting the AC Decoupling simulation. AC Decoupling simulation of the CAD software covers neither the impedance of VRM output nor the load IC’s input. The power net of interest and its reference net (current return path) are selected for analysis. Next, lumped analysis mode is chosen to compute the impedance profile that covers the power net throughout the entire PCB and the bypass capacitors connected to it.

The simulated plot of PDN impedance (i.e., impedance in ohm versus frequency in Hz) is shown in Figure 9. The impedance reaches its peak at the frequency range ~200 MHz, with magnitude of 2 ohm.

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Fig. 9. Simulated PDN impedance

Once the simulated PDN impedance meets the targeted impedance, the prototype PCB is fabricated and assembled with components.

IV. MEASUREMENT OF PDN IMPEDANCE

The PDN impedance of the prototype PCB is characterized by performing 2-port S-parameter measurement using vector network analyzer (VNA) E5071C from Keysight. Test setup of the 2-port S-parameter measurement is illustrated in Figure 10. Firstly, two female SMA connectors are mounted on the copper fill of the power net, as shown in Figure 11. Before the RF cables with the VNA ports are plugged to the female SMA on the PCB, calibration is performed using ECal N4431B from Keysight to compensate the loss and skew due to the RF cables.

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Fig. 10. Test setup of the 2-port s-parameter measurement (Keysight Technologies, 2014)

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Fig. 11. Mounting of SMA on PCB for test probing

Measurement of the s-parameter in 2x2 matrices (i.e., S11, S12, S21 and S22) is saved in Touchstone format. Subsequently, parameter S21 is extracted for mathematical conversion with Equation (6) [8] to impedance in frequency domain, which is conducted using Advanced Design System (ADS) from Keysight.

After the conversion, the measured PDN impedance is plotted (i.e., impedance in ohm versus frequency in Hz), as shown in Figure 12.

(6)

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Fig. 12. Measured PDN impedance

The measured impedance reaches its peaks of about 2 ohm at ~160 MHz and ~320 MHz respectively, which is well correlated with the simulated plot shown in Figure 9.

The simulated impedance differs from the measurement at low frequency range (i.e., below 20 MHz), which could be due to the behavior of the simulation models of the bypass capacitors imported for analysis. Furthermore, the measurement is performed on a PCB mounted with components, including VRM IC, versus the limitation in the CAD software that does not allow the inclusion of VRM’s effect during the simulation. Besides that, beyond 400 MHz, the measured PDN impedance maintains an uptrend in magnitude, due to the residual inductance of the SMA connectors mounted on the PCB and the parasitic inductance of the via. By eliminating the discrepancy, correlation is achieved between simulation and measurement.

V. SUMMARY

This article studies the strategies for good PDN design, and analysis of PDN impedance, in both simulation and measurement. These procedures are essential to ensure that the electronic device works properly as specified and meets the requirement of the EMC/EMI standards.

REFERENCE

[1] "Power Distribution Network Planning", by Barry Olney, In-Circuit Design Pty Ltd Australia [2] "Basic Concepts of Power Distribution Network Design for High Speed Transmission", by F.Carrio, V.Gonzalez and E.Sanchis [3] AN574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology, Altera [4] UG393: Spartan-6 FPGA PCB Design and Pin Planning Guide, Xilinx [5] Section 5: High Speed PCB Layout Techniques, High Speed Analog Design and Application Seminar, Texas Instruments [6] A Practical Guide to High-Speed Printed-Circuit-Board Layout, By John Ardizzoni [7] Application Note: Evaluating DC-DC Converters and PDN with the E5061B LF-RF Network Analyzer, Keysight Technologies [8] Application Note: Ultra-low Impedance Measurements Using 2-Port Measurements, Keysight Technologies