Voltage references have a long history of setting the precision standard for mixed-signal systems. Whether biasing an analog-to-digital converter (ADC) or digital-to-analog converter (DAC), the reference plays a vital role in driving the total system error. The IC design architecture, design techniques, and fabrication process are the primary internal factors which dictate the overall performance of voltage references. Specifications such as temperature coefficient, noise, thermal hysteresis, and long-term drift (LTD) are very important.

LTD is measured as the output voltage shift from a given voltage reference at power-up and then at selected intervals over time. Data is plotted in terms of parts per million.

Below is the theoretical formula of LTD:

LTD(ppm) = Max ([Vouttn – Voutt0}x1e6/Voutt0

where,

Vout = Voltage output of DUT

t0 = first hour of measurement

tn = nth hour of LTD data collection, where n can be as many hours as the voltage reference is powered-up

A voltage reference’s LTD is dependent on several factors: package stress due to package size, mold compound, PCB stress, and external environmental factors like temperature and humidity. With this information, the LTD(ppm) can be practically modeled as the below function:

LTD(ppm) = f(Voutt0 package stress, PCB design, PCB assembly quality, compound settling time, temperature, humidity)

Package stress

An analogy to package stress would be a pair of shoes. A comfortable pair of shoes would mean that the right shoe size was selected for the feet. If the shoes are too small, they are not as comfortable but seem to fit initially. However, over time the feet would begin to hurt as the shoe was not the right fit from the beginning. The same is true for semiconductor packages. If a die is crammed into a package that is not suitable for the die size, package stress will play a key role in the device’s performance over time.

Figures 1 and 2 are LTD plots for the same device in SOT-23 and ceramic packages.


Figure 1
LTD plot for SOT-23 package


Figure 2
LTD plot for ceramic package

PCB design

To mitigate solder joint stress, certain PCB designers use three-sided or four-sided PCB cut-out “slotting” techniques per site when designing LTD boards (Figure 3). The advantage of slotting the PCB is that it can thermally isolate the device under test (DUT) from surrounding circuitry, which can help reduce thermocouple effects and improve accuracy. A tab cut through the PCB on three sides of the voltage reference can reduce solder joint stress on the DUT. Measures were taken to ensure consistency of measurement from site to site and board.


Figure 3
Three-side cut-out “slotting” to relieve solder joint stress

Another way to reduce PCB stress is to bake the PCB through several temperature cycles before attaching the DUT. Then, prior to board power-up, the PCB with DUT soldered down undergoes a temperature cycle. This process is done to de-stress the PCB which has gone through reflow assembly. The temperature cycle occurs within a short duration after PCB reflow.

Bench test setup

A fully automated multi-site laboratory setup was developed to characterize the LTD of voltage references over a sample size which meets the statistical requirement for Gaussian analysis (Figure 4). The bench equipment is multiplexed by using onboard circuitry to power up, configure, and measure the Vout from different DUT sites, one at a time.


Figure 4
Multi-site voltage reference PCB

A chamber that provides environmental conditions, temperature, and relative humidity with corresponding temperature and humidity sensors add to the ability to monitor the setup (Figure 5). Automation ensures the consistency of setup configurations and reliable measurements and also reduces human error in post processing/data-logging. Pin and package-compatible variants can be tested using the same setup. The setup is backed by an uninterruptible power supply (UPS) to avoid the DUT reset in the event of power failure.


Figure 5
LTD bench setup

Data collected consists of voltage output measurements that are post-processed later to provide the LTD measurement for each device tested. The industry standard for voltage reference LTD is 1000 hours. Automation has created an ability to exceed that benchmark by monitoring and collecting data for as many as 10,000 hours (Figure 6). LTD data was taken from several of Maxim’s popular voltage references and the competition for comparison.


Figure 6
MAX6079 LTD over 10,000 hours

Reflow assembly

In industry, PCB assembly is usually done with solder reflow. This same approach is used in experiments. This ensures that all required components undergo the same specified temperature profile, minimizing errors of hand-soldering and prolonged elevated temperature exposure due to manual soldering.

[Continue reading on EDN US: Package compound settling]


Leo Apostol is a Senior Product Engineer working on voltage references, LED drivers, comparators, op amps, DACs, and ADCs at Maxim Integrated.

Sarvesh Miyan is a Director of Product Engineering at Maxim Integrated.

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