Current monitoring has become simpler because of the availability of dedicated integrated circuits. Current monitoring integrated circuits are readily available and under most circumstances do an excellent job, as do various instrumentation amplifiers, so building a current monitor using discrete devices may seem redundant, however there are circumstances where a circuit using discrete components might be the best approach especially if readily available low voltage parts can be used.

The circuit in this Design Idea resulted from the need to monitor current in both rails of a servo system’s +180/−180V power supply. Figure 1 shows the relevant part of the circuit for monitoring the negative rail. The circuit monitoring the positive rail replaces npn with pnp devices. Best results are obtained using inexpensive dual transistors and 1% resistors for setting Iref and for Re1 and Re2. Rsense should be 0.1% and adequately rated for power dissipation.

Figure 1 Circuit for monitoring the negative rail

Inspiration for this circuit and all those that use this topology derives from the current mirror topology and the notion that a varying current in Rsense, and therefore the voltage across Rsense, varies the current in Re2, and therefore the voltage across Rc1, in a linear fashion.

The circuit of Figure 1 owes its utility to Re1 and Re2. Making Iref fairly small and Re2 and Re1 very large and equal in value increases the voltage at the emitters relative to the voltage across Rsense. This in turn decreases the change in the output device’s Vce when the load is varied between no load and full load.

It is therefore possible by judicious selection of Iref, Re1, Re2, Rc2, and Rc1 to prevent Q2 being driven into saturation and also to not exceed the transistors maximum operating voltage. Bear in mind that hoe=I(collector)/VA (Early Voltage) implies that reducing the change in Ic also reduces the variation in β which in turn improves linearity. Rc is the sum of Rc1 and Rc2 so the ratio Rc1/Rc determines the offset at Vout−, under no load. The voltage generated across Rsense at full load determines the change in current in Re2 and Rc1 and therefore the full scale output at Vout−. Once a value for Iref is established, it is a simple matter to calculate the desired no load voltage across Rc and Rd. The effect of a varying Vce on Q2’s β is significantly reduced by the use of emitter resistors and inspection of the simulation data shows that the change in β has relatively little effect on the correlation between load current and output voltage. Using a configuration similar to a Wilson current mirror is probably unnecessary in view of the results achieved.

Figures 2 and 3 show alternative solutions for the constant current source to generate Iref. If Vss is stable and ripple free the constant current generator can be omitted, and a value of Rd can be selected to provide Iref.

Figure 2 An alternative solution for the constant current source to generate Iref.

Figure 3 FET bias is setup so that on startup Iref will not cause Vce or Vds to exceed the maximum value.

Figure 4 inverts Vout−, removes the offset, scales the output to the desired range, and can filter the output to deal with supply ripple or load spikes. The circuit can be simplified to just invert Vout− if a microcontroller with an ADC is used.

Figure 4 Inverting Vout− removes the offset, scales the output to the desired range, and can filter the output to deal with supply ripple or load spikes.

If VRe1 is at least 10 times greater than VRsense at full load, then the Q2 will not saturate and

VRsense =  (Iload + Iref) x Rsense                                             1

VRe1   = 10(VRsense(full load))                                                     2

Iref =IRe1 , and at no load i.e. Iload = 0 therefor:

Re1  = VRe1 / Iref  = Re2                                                           3

Vccs is the voltage across the constant current source and IRe1 = Iref to a close approximation, and Vbe can be taken as 0.6 to 0.65V:

Rd = (Vss – (Vccs + Vbe(Q1) + VRe1 )) / Iref                               4

Vce is the desired maximum voltage across Q2, and at no load. IRe2   is approximately equal to Iref,  therefor:

Rc = (Vss – Vce) / I(Re2)  ≈ (Vss – Vce) / Iref                             5

The desired offset voltage at Vout− at no load determines the value of Rc1:

Rc1 ≈  (Rc x Vout−(offset))  / VRc                                                6

An estimate of IRe2 at full load can be made because I(Rsense) is = Iref / 10:

IRe2(full load)  ≈  1.1 x Iref                                                          7

At maximum load current the full-scale value of Vout− is approximately:

Vout−(fullscale) – Vout−(offset) ≈ Rc1 x IRsense(full load)               8

LTspice was used to produce the following curves to show the circuit’s linearity, the effects of filtering, and Vce and Vds during circuit operation. The load current ramps from 0 to 1 amp and the output voltage is overlaid on the load current. The results are similar to the actual circuit performance. Filtering prevented trips due to short duration spikes in the load current. Isolation may not be necessary but should always be considered when designing high-voltage circuits.

Figure 5 Vout without 25nF cap at C1 in Figure 4

Figure 6
Vout with 25nF cap at C1 in Figure 4

Figure 7 Voltages on the active devices

For some background on current mirrors and the Widlar and Wilson current source, see:

Seagan Yi-O'Kelly has a background in plant automation and analog design.