Last April at ESA's SEFUW conference, I discussed the first design-in experiences of Xilinx's next FPGA for space applications, the 20 nm Kintex UltraScale XQRKU060. The new space-grade device will enable future ultra high-throughput applications and will contain the same die as the current commercial equivalent, but its silicon will be 'locked-down' to provide more assurance and traceability for space customers.

In terms of raw performance, the XQRKU060 is many generations ahead of the radiation-tolerant XQRV4QV and radiation-hardened XQRV5QV space-grade FPGAs currently offered by Xilinx. Its speed and range of logic resources greatly exceeds the capability of all existing SRAM, anti-fuse, and flash-based qualified PLDs.

Table 1 Comparison of Xilinx SRAM-based space-grade FPGAs

The fabric of the XQRV4QV is based on the traditional Xilinx configurable logic block (CLB), slice and logic cell hierarchy to implement sequential and combinatorial logic. Each CLB contains a total of four slices, eight LUTs, eight flip-flops, eight MULT-ANDs, two arithmetic & carry chains, 64 bits of distributed RAM, and a 64-bit shift register. The XQRV4QV targeted a system performance of 350 MHz and compared to previous FPGAs, the Virtex-4 introduced higher levels of dedicated DSP capability. Four different XQRV4QV parts are offered, SX55, FX60, FX140, and LX200, varying in size and the number of resources, with both FX versions also containing dual embedded PowerPC 405 RISC cores.

For the radiation-hardened XQRV5QV, to provide higher performance and better utilisation of the FPGA micro-architecture, each CLB contains a pair of independent slices containing a total of eight 6-input LUTs, eight flip-flops, two arithmetic & carry chains, 256 bits of distributed RAM and a 128-bit shift register. The XQRV5QV targeted a system performance of 450 MHz and a 30% lower-static power version was introduced through device screening in 2018.

The Kintex UltraScale fabric extends the Xilinx micro-architecture to deliver a step-change increase in bandwidth, capacity, and integration, enabling the space industry to avail of GHz, ultra high-throughput on-board processing. This capability will allow satellite operators to offer many new applications such as real-time, SUHD, Earth-Observation remote sensing, broadband telecommunication transponders, digital payload space-based internet, and IoT.

The Kintex UltraScale architecture has improved communication, clocking, critical paths, and interconnect within its fabric to deliver Tb/s, ASIC-class system-level performance for the most demanding of applications requiring low-latency, ultra high-throughput I/O, memory bandwidth, data flow, processing, and DSP.

Figure 1 The UltraScale architecture
Source: Xilinx

Each UltraScale CLB contains one slice providing eight 6-input LUTs and 16 flip-flops to implement sequential and combinatorial logic and routing more efficiently. Every LUT output can connect to slice outputs, or optionally be registered in a flip-flop or a latch. The storage elements can also be driven by direct inputs to the slice or by the results of the internal carry logic or wide multiplexers. The XQRKU060's CLB architecture improves logic and routing, provides more flexibility and allows for greater optimisation of designs.

A 20 nm FPGA allows OEMs to implement higher-bandwidth satellite and spacecraft IP optimising performance together with power consumption. Using a core voltage of +0.95 V, from the XPE spreadsheet, populating 70% of the resources predicts an overall dissipation of ~8 W. Previous SRAM-based, space-grade FPGAs targeted performance resulting in high power dissipation due to large amounts of static current, hardened, duplicated configuration memory cells and/or triplicated logic. This made procuring suitable, space-grade POL regulators for the core voltage difficult and unaffordable for many manufacturers.

Both the plastic commercial and the ceramic space-grade versions of the KU060 can be designed-in to have the same PCB footprint. For the latter, a 40×40 mm 1509-pin CGA is compatible with the commercial A1517 pin-out and Xilinx has released the following advance information regarding caveats (please note this is subject to change so contact Xilinx for the latest details).

Table 2 Differences between XCKU060 and XQRKU060 pin-outsSource: Xilinx

For reliability reasons, the corner pins of the XQRKU060 have not been connected and one high-speed transceiver has been moved from pins AV1/AV2 to T1/T2 respectively as highlighted below. A VCCINT sense line has also been added to allow direct measurement of the core voltage.

Figure 2 Pin-out of the ceramic XQRKU060
Source: Xilinx

Ceramic packages have larger physical volumes than their plastic equivalents resulting in higher parasitics, increasing power-distribution voltage drops. Subsequently, for the XQRKU060, Xilinx is recommending the following elevated nominal supplies for the key power rails with a tolerance of ±2%. The advance datasheet will become available for download from the secure Space Lounge at the end of March.

Table 3 Recommended increased supply voltages for the ceramic XQRKU060Source: Xilinx

At a hardware level, for linear or switching POLs, the increased supply rails can be realised by changing the value of a resistor allowing sub-systems to re-use the same FPGA design, layout, and power distribution throughout all stages of spacecraft development. The new specified power rails for the XQRKU060 meet lifetime reliability requirements.

Initial radiation testing by NASA, Sandia National Laboratories, and the Lawrence Berkeley National Laboratory reports a total-dose tolerance of 120 kRad (Si) and SEL tolerance up to 79.2 MeV-cm2/mg. This was the maximum ion energy offered by the cyclotron and not the minimum sensitivity of the part, and further testing is planned by the Xilinx Radiation Test Consortium (XRTC). CMOS scaling has intrinsically made the part less susceptible to total-dose and latch-up effects, the layout of the configuration memory cells has been optimized using SEU design rules to protect against multiple-bit upsets, and users can triplicate logic and add EDAC to memory to bolster overall radiation hardness manually or using industry-standard tools from Mentor Graphics or Synopsys.

To complement the XQRKU060, Xilinx also offers its MicroBlaze fault-tolerant, fail-safe, 32-bit RISC CPU, which can be instantiated within the KU060. This soft IP has been implemented using a triple-redundant voting scheme (TMR) as shown below.

Figure 3
Fault-tolerant, fail-safe, TMR MicroBlaze block diagram
Source: Xilinx

The commercial-grade XCKU060 FPGA is a mature part that can be procured today with first samples of the ceramic XQRKU060 available at the end of 2019. QMLY qualification is targeted for September 2020.

Both the XCKU060 and the XQRKU060 implement IP using the Vivado Design Suite, which has been developed to optimise the physical realisation of large, Tb/s, low-latency, ultra high-throughput I/O, wide bus, large memory-bandwidth applications. Traditional placement and routing use simulated-annealing algorithms which do not scale for million-LUT designs, nor account for total wire length or congestion. Vivado uses a multi-variable cost function to find a routable solution at device utilizations of greater than 90% without impacting performance.

Spacechips has designed-in the XCKU060 and the XQRKU060 using Mentor Graphics' xDxDesigner/Expedition PCB flow and future articles will include reference designs discussing in-orbit re-configuration; readback and scrubbing; partial re-configuration; the use of Xilinx's SEM IP to detect, correct, and classify SEUs to reduce FIT rates and improve device reliability; configuration-memory fault injection to test and architect a SEFI mitigation strategy; how to configure and clock the FPGA; power distribution; and the selection of similarly-qualified companion parts.

Spacechips also teaches, demonstrates, and compares the XCKU060 implementing IP with other space-grade FPGAs on its space electronics training courses around the world. We will be teaching in Bremen, Germany at the end of March, Los Angeles this April, and Colorado Springs in May. Until next month, the first person to tell me the difference between soft and hard IP will win a Courses for Rocket Scientists World Tour t-shirt. In this context, hard does not mean resistant to radiation effects. Congratulations to Gillian from Montreal, Canada, the first to answer the riddle from my previous post.

Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides ultra high-throughput on-board processing products, design consultancy in space electronics, training, technical-marketing, and business-intelligence services.