Efficiency is often the most important factor when designing a power supply for many types of consumer and industrial applications including mobile phones, tablet and notebook computers, rechargeable power tools and LED lighting, and a myriad of other products.  High efficiency may be required to meet legislative requirements, or simply to reduce the dissipated heat and thereby enable the design of smaller & lighter end products. Choosing a synchronous MOSFET to meet all of the requirements can be a bewildering task.

Naturally, engineers will look at the obvious datasheet parameters first, selecting devices with the right voltage and current ratings . Because efficiency is important most devices are primarily selected by RDS(on).  Depending on the switching frequency, then the dynamic parameters; for example, gate charge, Qg and Qgd, can be a good indicator of the expected gate losses. The Qg Figure Of Merit (FOM =  RDS(on) x QG) is also a good indicator of a MOSFET’s efficiency in a switching application, and the MOSFET’s capacitance, Ciss, Coss, Crss, can predict whether drain-source spiking and gate bounce will be a problem. Low capacitance can contribute to higher efficiency also. Finally, the device must fit into your design, so you look at how big it is and what package it comes in. 

However, there is another parameter, Qrr, that is often ignored, and is usually found at the bottom of the datasheet. In applications where current flows through the MOSFET’s body diode, for example, in a synchronous rectifier and in free-wheel applications, then the reverse recovery charge, Qrr, causes some significant challenges which the design engineer needs to carefully address.

Qrr or reverse recovery charge is the charge that accumulates in the PN junction of a MOSFET’s body diode when the diode is forward biased. In most applications, current flows through the body diode twice for each switching cycle, causing charge to accumulate. The later dispersion of that charge, either within the MOSFET itself, or as an additional current (Irr) which flows briefly through the high-side MOSFET, and causes additional losses in the system.

A spiky character
That reverse recovery current (Irr) also interacts with the PCB’s parasitic inductance, to cause spikes in the drain-source voltage (VDS). These spikes can be reduced by reducing the PCB’s inductance or by choosing a MOSFET with low Qrr.  Failure to address the spiking issue at the design stage often results in engineers having to use a higher voltage grade, and therefore more expensive MOSFET later in the project.

But that still leaves a problem. If left untreated, then spikes at the drain pin can be capacitively-coupled to the gate pin, leading to so-called ‘gate bounce’. If this gate bounce exceeds the MOSFET’s threshold voltage, then cross-conduction occurs and the MOSFET can turn on when it should be off. If both the high-side and low-side MOSFETs turn on at the same time, shoot-through current occurs between the power rails causing major power losses and potentially destroying the MOSFET.

Let’s look at this in more detail. Due to the dead-time needed in most applications, current flows through the body diode twice for every switching cycle. Let us first consider what happens just before the sync-fet is turned on. Since current will be flowing through the body diode during the dead-time, then some of the load current becomes trapped as stored charge, Qrr.

As the sync-fet is turned on, then the stored charge is dissipated internally within the MOSFET. Therefore, a proportion of the load current is lost due to the Qrr effect and contributes to I2R loss within the sync-fet.

In the second instance, the MOSFET’s body diode becomes reverse biased once again when the high-side MOSFET turns on. Additional current, Irr, flows briefly through the high-side MOSFET until the stored charge, Qrr, is fully depleted. The charge depletion is not instantaneous, Irr typically flows for a few tens of nanoseconds until Qrr is depleted. The reverse recovery time, Trr, is quoted on the datasheet. In this case, then Irr results in additional I2R losses within the high-side MOSFET, as shown in Figure 1.

Figure 1 Irr results in additional I2R losses within the high-side MOSFET

Vds spiking
Reverse recovery current spike, Irr, also interacts with the PCB’s parasitic inductance to create a voltage spike where:

V = L x (di/dt).

The MOSFET should be suitably rated to ensure that the breakdown voltage rating (BVDS) is higher than the maximum spike; typically an 80% derating is applied. An application with a measured 80V Vds spike would typically require a MOSFET with a BVDS voltage of at least 100V.

[Continue reading on EDN US: Gate bounce]

Mike Becker is Product & Marketing Manager at Nexperia.

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