Introduction of crosstalk

Crosstalk is an unintentional electromagnetic (EM) field coupling between transmission lines on PCB. This phenomenon becomes a major culprit in signal integrity (SI) contributing to the rise of bit error occurrence in data communication and also electromagnetic interference (EMI). With the existence of mutual inductance and capacitance between two adjacent transmission lines on PCB, crosstalk becomes more severe nowadays due to the higher slew rate. The crosstalk is further intensified on compact PCB where signal traces are routed more closely to each other due to limited board space.

With reference to Eq. (1) [1], crosstalk can be minimized by reducing the dielectric thickness between PCB trace and reference plane [1] [2]. This article zooms into observing how the PCB dielectric thickness affects the signal crosstalk. The crosstalk analysis is carried out in frequency and time domain using Mentor Hyperlynx.

Fig 1

(1)

D = spacing between PCB traces H = dielectric thickness between PCB trace and reference plane

Crosstalk analysis in frequency domain

In this study, four transmission line models in single ended mode on outer (i.e., microstrip) and inner (i.e., stripline) PCB layers are built in Hyperlynx based on varying PCB dielectric thickness. Fig. 1 depicts the crosstalk simulation topology in frequency domain using Hyperlynx for each transmission line model listed in Table 1, with transmitting and receiving end of aggressor line assigned as port P1 and P2 respectively, while transmitting and receiving end of victim line assigned as port P3 and P4 respectively. The coupled spacing and length between the aggressor and victim are set one and a half time the trace width and 1.5-inch respectively.

Fig 2

Fig. 1. Crosstalk simulation topology in frequency domain for transmission line models listed in Table 1

These four transmission line models are laminated with medium loss substrate material (i.e., Dk 3.6 and Df 0.01). Each model has trace thickness 1.2 mil. Model 1A is set as microstrip, substrate thickness 3 mil and trace width 7 mil to achieve characteristic impedance 45.1 ohm. Meanwhile, model 1B has the same parameter setting as 1A except substrate thickness is increased to 4 mil, to achieve characteristic impedance 53.7 ohm. The substrate thickness of model 1B is increased by not more than 1 mil versus model 1A to limit the trace impedance of both models within ±10 % tolerance of the nominal 50 ohm. The interest of this study is on varying substrate thickness, hence the other parameters of both model 1A and 1B shall remain the same.

Table 1: Transmission lines in single ended mode for varying dielectric thickness modeled in Mentor Hyperlynx

Table 1

On the other hand, model 2A in table 1 is set as symmetrically centered stripline, trace width 5 mil, substrate thickness between trace and upper/lower reference plane 5 mil, to achieve characteristic impedance 45.7 ohm. Meanwhile, model 2B has the same parameter setting as 2A except substrate thickness between trace and upper/lower reference plane is increased to 7 mil, to achieve characteristic impedance 54.8 ohm (i.e., within ±10 % tolerance of the nominal 50 ohm).

By field solving the 4-port simulation topology depicted in Fig. 1, S41 parameter that represents far end crosstalk of the transmission line models in Table 1 are plotted in Fig. 2. Most data communication protocols in embedded system are source synchronous, where high speed signals propagate in the same direction at any one time. Hence, we are concerned about the ratio of induced noise at victim’s receiving end to the injected signal at adjacent aggressor’s transmitting end (i.e., S41 parameter). A more severe crosstalk is indicated by smaller absolute value in dB.

With reference to Fig. 2, across the wideband up to 2 GHz, S41 for model 1A is about 3 dB lower versus 1B. Similarly, S41 for model 2A is at least 5 dB lower versus 2B. This result indicates that for both microstrip and stripline in single ended mode, thinner substrate or dielectric between PCB trace and adjacent reference plane reduces the signal crosstalk.

Fig 3

Fig. 2. Plots of far end crosstalk in frequency domain for transmission line models listed in Table 1

Crosstalk analysis in time domain

The crosstalk analysis in time domain is continued for transmission line models listed in Table 1, with topology depicted in Fig. 3, where transmitter of the aggressor signal toggles at 333 MHz. On the othe hand, the transmitter of the victim signal is stuck low to remain as a quiet line.

Fig 4

Fig. 3. Crosstalk simulation topology in time domain for transmission line models listed in Table 1

The noise induction on the receiver of victim signal due to the toggling signal on aggressor is shown in Fig. 4. On microstrip, i.e., model 1A versus 1B, the crosstalk magnitude is reduced by 24 mVpp when thinner substrate is applied. Meanwhile, on stripline, i.e., model 2A versus 2B, the crosstalk magnitude is reduced by 45 mVpp when thinner substrate is applied.

Fig 5

Fig. 4. Noise induction on receiver of victim lines for transmission line models listed in Table 1

Summary

The study effort in this article proves that crosstalk can be minimized by reducing the dielectric thickness between PCB trace and the adjacent reference plane. This implementation is essential to reduce unintentional coupling on compact PCB with tight inter-trace spacing due to limited real estate.

References

[1] B. Olney, “Signal Integrity, Part 2”, The PCB Design Magazine

[2] "High-Speed Board Layout Guidelines"