One popular way to reconstruct analog signals in microcontrollers (µCs) is through pulse width modulation (PWM). However, this modulation produces a large number of harmonic components, which limits the bandwidth of the generated signal and requires filtering to reduce output ripple (see Cancel PWM DAC ripple with analog subtraction and Fast PWM DAC has no ripple).

Nevertheless, because it is an on-off modulation, PWM has the advantage of needing only a simple binary output. Another option is to have a specific digital-to-analog (DAC) peripheral with a certain number of bits of resolution. Both the DAC and the PWM options call for use of a specific peripheral, which in many cases is not available.

One solution is to use an 8-bit microcontroller combined with a 4-bit fixed voltage reference (FVR) module to generate an analog signal using sigma-delta modulation (SDM) (Reference 1). Because the SDM can move the noise to higher frequencies, the filtering task is easier. Thanks to this effect, a resolution gain is achieved, and the effective number of bits is increased. Figure 1 shows the first order SDM block diagram and Figure 2 shows the assembler code:

Figure 1 First order 4-bit sigma-delta modulator
Figure 2 Assembler code for the modulator

The output voltage (V) is truncated to connect the four most significant bits (MSB) to the 4-bit DAC module, and the residue, h, is added to the next input sample, x. As this simple SDM admits only the half input range to avoid saturation, the data input amplitude is limited to 7-bits, and its MSB is fixed to ‘0’. To test the design, a look-up table of 128 sine points sampled at 32 kHz by the timer 1 interrupt is used. Timer 0 is used to generate the main interrupt, which executes the SDM code at a rate of 250 kHz. The CPU clock is configured to 64 MHz and the time spent by the modulator is less than 2 µs. Figure 3 shows the analog output response time.

Figure 3 Waveform of the generated signal before filtering

Moreover, Figure 4 shows the amplitude response in the frequency domain for the generated signal by directly sampling the 4-bit output with a logic analyzer. It can be concluded that 60 dB of spurious free dynamic range can be achieved with a low pass filter removing the noise above 1 kHz, which implies an oversampling rate (OSR) of 250 and a resolution gain of 4 bits (0.5*log2 OSR). This solution is also valid for fewer output bits, even if only one (1) on-off output bit is utilized.

Figure 4 Output frequency response (128 ks DFT)

Reference

  1. Understanding Delta-Sigma Data Converters, R. Schreier and G.C. Temes, IEEE Press, John Wiley & Sons, Inc., 2005