Don't let misconceptions about circuits and their return currents ruin your day, and your design, for there's an exercise to try.
Once upon a time, you studied the electric circuit theory where you learned many techniques to analyze electric circuits. Two famous and analogous techniques are the nodal voltage analysis, and the mesh analysis. In the nodal voltage analysis, you started by picking a node that becomes the reference node. This node is assumed to have an absolute zero potential, which we often call the “ground” node.
You won’t find this assumption harmful so long as you don't care about the voltage relationship between the circuit and other objects. The node that is common between many sub-circuits is usually a very good selection to mathematically simplify the circuit analysis.
When we study the specialized courses of electronic circuits, we usually forget about many circuit analysis techniques such as superposition, the Thevenin Equivalent, the Norton Equivalent, and mesh analysis. We focus mainly on one technique, the nodal voltage analysis (Figure 1).
After years of that deep focus as a student and as an engineer, you may forget some fundamental concepts in electric circuit theory. This is when fatal misconceptions infiltrate our minds.
The ground node is often thought of as a physical graveyard for all charges.
It is certainly not. The ground node is merely a node that we personally choose. It has nothing special other than usually being common with many sub-circuits. Being a common node doesn't add special physical properties. The only stored charges at the ground node are the negative plate charges of capacitors that have one of its terminals connected to ground. All other charges circulate in the circuit, and never come to a stop (Figure 2). Remember, all currents flow in a loop and charges return to their source.
The ground node is a safe haven from noise. Most of the different noise currents, however, pass through the ground node (Figure 3). For only well-designed ground rails, however, the impedance of the rail is negligible, such that the noise potential difference across the rail is almost zero.
There is a common belief that separating the ground pads of two interacting domains protects the quiet domain from the noisy one. This can be one of the worst crimes that an RF engineer may unknowingly commit. Separation of the ground pads may in many cases result in severe noise coupling from the noisy domain outputs to the inputs of a quiet domain. You may find this counter-intuitive, but it becomes clear when picturing the complete circuit with the bond wires, up to the PCB level, as in Figure 4. A similar action occurs as well when all MOS bulk ties are connected to a dedicated ground pad.
In power-aware digital design, floating outputs are not only associated with switching off the ground path, but with switching off the supply path as well (Figure 5). The physical design preference usually favors switching the ground path. This is because an NMOS device would then be used, which has less area than a PMOS device for the same ON resistance.
The ground and supply rails may seem irrelevant to timing closure. Timing closure is concerned with different cells delay and different signals edges. When a ground rail has relatively high impedance, considerable IR drop results across the supply and ground rails, which reduces the effective supply voltage and thus increases CMOS cells delay. Moreover, even if the average IR drop on the rail is insignificant, switching noise currents can create significant transient noise voltage across the ground rail. Thus, as illustrated in Figure 6, the signal edge that arrives at a distant gate from the signal source can effectively “move” in time . The time shift depends on the transient noise magnitude and polarity. This effect becomes more evident for high rise/fall time signals.
To separate or not to separate?
That is the tricky question. One important item that needs elaboration is the separation of ground pads. The section above may give the impression that ground-pad separation is a bad design practice, although it could be a common practice in many chips. In general, designing a single unified ground connection with low resistance and low inductance is much better than designing multiple ground rails with their associated hassle of complex return current paths between interacting domains, and magnetic coupling of large-area loops carrying high-frequency currents.
In special cases, however, you can't avoid ground pad separation. For example, suppose you have a crystal oscillator, and a noisy digital block that both share one ground pad as in Figure 7. The digital block draws noisy currents from the supply, which return through the ground rail and bond wire. Therefore, significant voltage glitches exist across the ground bond wire. As this bond wire is common with the crystal oscillator ground, the noise voltage glitches will be effectively added to the crystal pure sinusoidal voltage at the oscillator internal nodes.
In such cases that require separation, do the following:
- Place as many decoupling capacitors around the noisy block as possible (Figure 8). This diminishes the transfer of the noisy supply currents outside silicon and thus minimizes the noise voltage created across the block rails and its outputs.
- Minimize the electrical interaction, or simply the transferred current, between the noisy block and other blocks. To achieve that, use drivers with relatively high output impedance in the noisy domain and high-input-impedance buffers in the quiet domain.
The ground node is merely a node of definition that only facilitates circuit analysis. All currents travel in loops and do not stop at the ground node.
To anticipate and resolve the ground-related issues, simply picture the complete circuit with all physical connections without the ground node definition. Visualize the different current loops and common paths.
Before making the design decision of unifying or separating the ground pads of different domains, perform a careful study of the anticipated gain and potential impact.
Here's an exercise. The left side of Figure 9 shows a simple NMOS current source with a finite drain impedance. What is the low-frequency AC impedance seen by the supply voltage source?
The answer is fairly simple. Now let us keep the circuit physically the same but choose the NMOS drain to be the ground node rather than the NMOS source, as in the right side of Figure 9. Would the impedance stay the same? Never let the ground elude you.
- Maxim Integrated Application Note #4345, “Well Grounded, Digital Is Analog”
Mohammed Tawfik AbdelHafez is a Senior Principal Engineer in the Technology team at Si-Vision.
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