A high performance ternary DAC implementation from DAC-master Stephen Woodward.

TritNoun (plural trits) (computing) The ternary equivalent of a bit; a fundamental unit of information that may take any of three distinct states.

EDN Editor-in-Chief Michael Dunn recently posted an interesting article on his *BenchTalk* blog, “**Ternary DAC: Greater resolution, less bits**,” that explores the interesting idea of squeezing more than just the usual single bit of information from port pins that can be individually programmed for both output and tri-state (i.e., 0, Hi-Z, 1), correlating with ternary (trit) values (0, 1, 2). Since, from an information-theoretic point of view, 1 trit ≈ 1.58 bits, this makes perfect sense, with, for example, just 5 trits closely approaching the resolution of 8 bits.

From an old analog designer’s point of view however, the fun part is then translating that theory into an accurate output, while accommodating such real-world complications as temperature variation, single rail power supplies with noise and variation, etc. Michael’s article illustrates several interesting approaches. Here’s another:

**Figure 1**Ternary DAC combines discrete transistors with shunt reference.

My Design Idea uses discrete transistors to sum ternary-weighted currents (1, 3, 9, 27, 81 µA) from each of five trit pins as controlled by associated precision resistors. Each resistance is determined by the ratio of the current weighting of its particular trit to the voltage reference applied across it, according to the following design equation, for *t = 0, 1, 2, 3, 4…*

R_{t} = 1M·(2V − 0.06·log_{10}(3^{t})) / 2V / 3^{t}_{ }[1]**
**

Readers may recognize the *0.06·log* term as the familiar diode equation for voltage across a forward-biased bipolar junction (in this case, the emitter/base junctions of the 2N5087s), which here accounts for the effects on V_{BE} of the different currents sourced by each DAC trit. The *2V* terms come from the LM4040 reference, providing an accuracy-improving PSRR limited mainly by the 2N5089 emitter-follower impedance working into its 20kΩ bias resistor:

PSRR = 20kΩ / (26mV / 120µA) = 39dB [2]

Substituting standard values from **Figure 1** for those calculated in [1] yields the not-too-shabby predicted performance in **Figure 2**, which includes good monotonicity, integral linearity, and accuracy.

**Figure 2**Ternary DAC has good linearity and monotonicity.

**Figure 3**A closer look at the integral nonlinearity: volts on right axis.

None of which, of course, addresses obvious questions about the practicality or cost-effectiveness of such a parts-count-intensive approach for saving a few port pins in the face of numerous alternatives for multiplexing ordinary binary outputs into various cheap and readily available monolithic DAC chips. Which, come to think of it, is probably a good thing.

Maybe not all enjoyable puzzles have to be practical?

**Related articles**:

- Hybrid PWM/R2R DAC improves on both
- Three paths to a free DAC
- Mutliplexing technique yields a reduced-pin-count LED display
- Technique increases low-cost DAC's resolution
- Ternary DAC: Greater resolution, less bits

—*W. Stephen Woodward** is one of EDN's most prolific and innovative Design Ideas authors, with dozens of contributions to his credit.*