To deliver the next generation of satellite services, spacecraft manufacturers are exploiting ultra deep-sub-micron semiconductors. There are many qualification and procurement options available to OEMs based on a mission's reliability needs.
To deliver the next generation of satellite services, spacecraft manufacturers are exploiting the integration, on-board processing, and power consumption advantages of ultra deep-sub-micron semiconductors.
Many NewSpace companies are baselining commercial-grade semiconductors typically fabricated for producing high yields with large densities, fast speed, and low power for consumer applications within a terrestrial environment, e.g. a lifetime between five to ten years and an operating temperature range from 0 to +70°C.
To provide better reliability, some NewSpace companies are using industrial or automotive-grade semiconductors with an extended temperature range from −40 to +110°C.
To provide further product assurance and traceability for space users, Enhanced Plastic guarantees parts from −55 to +125°C as well as batch management, e.g. no variation between foundries, lots, and wafers. Some silicon vendors also offer QCOTS and COTS+ components which have been up-screened to a higher level of reliability to address known failure mechanisms for plastic parts. Burn-in tests identify and eliminate juvenile rejects, and there are checks for humidity and out-gassing, as well as X-ray and C-SAM inspection to verify the integrity of the construction of the microchip. Formal standards exist for each of these assessments and some are carried out on a complete lot, whereas destructive investigation such as radiation testing is performed on a small sample.
To ship plastic parts, devices are first placed into specific ESD trays, strapped between ESD plates, dessicant packs, and a humidity-level indicator added before being placed into a hermetic vacuumed bag. Finally, ESD protection forms provide protection against shock and vibration prior to boxing as shown below.
Figure 1 Packaging plastic parts for shipment
As an example of a screening and qualification flow to deliver plastic-packaged semiconductors for space applications, Teledyne e2v offers commercial-grade, multi-core, PowerPC, or ARM-based microprocessors fabricated using a 45 nm SOI process as shown below. These can be delivered to the NASA qualification flow for plastic devices screened to eliminate early failures including static/dynamic burn-in, temperature-cycling, and accelerated-stress tests, as well as visual, X-ray, and C-SAM inspection to confirm the manufacture. Formal standards exist for each of these checks, e.g. MIL-STD-883, JESD22 etc. Depending on your mission's reliability needs (continuous-availability GEO telecommunication, LEO small-satellite constellation, or short-duration CubeSat), three different screening (quality) options can be procured.
Figure 2 Teledyne e2v plastic-packaged, commercial-grade microprocessors
Traditional satellite manufacturers procure for existing builds such as EM, EQM, and FM. It's very supplier specific, but in some cases, engineering samples for prototyping have only been tested at an ambient +25°C (please check with your provider!). Representative EQM parts will have been characterised from −55 to +125°C and completed many of the standard qualification tests. Flight-grade components will have completed the full qualification flow according to some certified quality level such as QML or ESCC.
To ship high-reliability ceramic parts, devices are first placed into specific ESD trays, strapped between ESD plates before being placed into a hermetic vacuumed bag. ESD protection forms provide protection against shock and vibration prior to packaging. Flight-grade components, together with a certificate of conformance and a data pack, are placed in a container which is then strapped and sealed as shown below.
Figure 3 Packaging ceramic, space-grade parts for shipment
As an example of a screening and qualification flow to deliver space-grade, hermetic, ceramic-packaged semiconductors, Teledyne e2v offers broadband ADCs and DACs as shown below. These can be delivered to either QMLV SMD or ESCC EPPL, which include endurance tests to eliminate early failures, e.g. burn-in and accelerated lifetime, as well as non-invasive and destructive electrical, mechanical, and thermal checks to confirm device construction, like loose particles (PIND), ESD, vibration, and micro-sectioning. Formal standards exist for each of these assessments, such as MIL-STD-883, MIL-PRF-38535 etc. with the range of screening increasing from EM to EQM to FM.
Figure 4 Teledyne e2v hermetic, ceramic-packaged, space-grade ADC and DAC
For non-hermetic ceramic packages, a new DLA QMLY certification has been created to eliminate failures including wafer-lot acceptance tests, PIND checks, temperature cycling, accelerated burn-in, extended life, as well as X-ray/C-SAM inspection to verify the integrity of the assembly. Formal standards exist for each of these assessments (MIL-STD-883, MIL-PRF-38535), with the range of screening increasing from EM to EQM to FM. To be ESCC 9000 compliant, a minimum of 111 die from each lot have to be considered before devices can be formally certified and included in the EPPL.
Figure 5 Non-hermetic ceramic-packaged, 90 nm SOI, GHz microprocessor
You can download or order a free poster that lists and compares screening levels for the various quality grades here. Until next month, the first person to tell me why BME ceramic capacitors are increasingly being used on semiconductors will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to John from Dallas, USA, the first to answer the riddle from my previous post.
Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides on-board processing products, design consultancy in space electronics, technical-marketing, training and business-intelligence services to the global space industry. Spacechips is helping companies around the world select the right components for future missions and we will be teaching three-day courses on Space Electronics in Madrid, Spain this September and Los Angeles in NovemberRelated articles:
- Introducing the first 16 nm semiconductor for space applications
- Qormino: A compact, multicore processing system solution
- Understanding and comparing the differences in ESD testing
- Burn-in 101
- 1st space tourist takes off, April 28, 2001
- Launch plane for private spacecraft unveiled, July 28, 2008
- SpaceX and the new space race