In "Is PAM4 really necessary?", I shared an earful from Lee Ritchey on why 4-level pulse amplitude modulation (PAM4) may not be the solution to high data rate signaling. To get another perspective, I asked Keysight's Rick Eads. Rick plays a big role on the physical-layer peripheral component interface express (PCIe) standard. PCIe will not be adopting PAM4 for the 32 Gbps generation 5 PCIe. Given Rick's tremendous integrity, I trust him to offer an unbiased view of the PAM4/NRZ landscape.

In case you don’t know Rick, I consider him one of the most generous engineers in the field of high-speed serial technology. If you bump into him at an industry event and ask him a question, have your notebook open and pen poised because you’ll want to record his insights.

Rick’s job title is Principal Computer I/O Segment Manager. I don’t know what that means, but I’ll testify that he knows the deep ins and outs around PCI Express, NVMe, and just about every high speed electrical technology.

In a nutshell, PAM4 is replacing so-called NRZ (non-return to zero) signaling in many, but not all, 30+ Gb/s applications. NRZ is the baseband, logic-emulating modulation scheme with high 1s and low 0s—it should be called PAM2 because there are two levels and the signal is modulated by varying its amplitude. on the other hand, PAM4 has four levels, each of which encodes two bits. With twice the data per symbol, PAM4 uses half the bandwidth of NRZ at the same data rate. When I asked Rick the below questions, he responded within an hour, “Do you want my opinion, Keysight’s opinion, or PCISIG’s (PCI Special Interest Group’s) opinion?” My answer was: “I want the unvarnished Rick Eads, of course!” And, as you’ll see below, I got it.

EDN: How committed is PCIe to NRZ or PAM4 (or whatever) for Gen 5 and 6?
Eads: The PCISIG (PCI special interest group—the people who define the standard) went with NRZ for Gen 5 to meet a quick timeline that would ensure PCIe would be able to support the bandwidth requirements for 400G Ethernet. The short timeline is key here. By choosing NRZ, the PCISIG was able to leverage most of the test [equipment] collateral and methods that were developed for Gen 4. One way to think of Gen 5 is: Gen 4 but with only the additional features necessary to support 32 GT/s [in PCIe-speak, a “transfer” includes both data bits and overhead bits] operation.

If the PCISIG had decided to go with PAM4 for Gen 5, it would have had to develop, test, and validate new methods for things such as stressed receiver calibration. This could have easily added a year or more to the development timeline. Right now, PCIe 5.0 is slated to reach the 1.0 revision level in 2019.

Which signaling technology will be used beyond PCIe 5.0 is anybody’s guess. I think the big considerations are receiver capabilities, board material costs, and connector choices. In the end, it comes down to what kind of channel PCIe Gen 6 will support. How many connectors? Which connector is used? Thus, there are a lot of things still up in the air that could drive the choice for Gen 6 signaling to PAM4, NRZ, or something else entirely.

EDN: In the current environment of PCB dielectric, is PAM4 necessary at 56 Gbps, 112 Gbps, etc. or do you think it's possible to stick with NRZ?
Eads: PAM4 has demonstrated it’s applicability in certain applications today: in OIF-CEI 4.0 (optical Internetworking Forum—Common Electrical Interface) and IEEE 802.3bs, 802.3bj, etc.

I think channel length and channel signal quality are key determinants of what kind of signaling is used. Engineering is a collection of tradeoffs. NRZ is reasonably simple but you must accommodate a higher Nyquist frequency in the channel. PAM4 can give you twice the data rate for a given baud rate, but the dynamic range is compressed because where you had only one eye. Now, you have four logic levels and 3 eyes. It adds a lot more complexity to the receiver clock data recovery (CDR) circuit and requires greater sensitivity within the receiver to accurately determine each of the four logic symbol levels.

One thing that PAM4-based systems typically include in the receiver design, in addition to aggressive equalization, is forward error correction (FEC). This lets the PAM4 link operate effectively at much higher bit error ratios (BERs) compared to similar NRZ based systems. Where in PCie, for example, the link operates at a BER of 1E-12, PAM4 systems are fine operating at 1E-6, 1E-5. Using FEC, the PAM4 systems are able to ultimately match or exceed the 1E-12 BER of similar signaling standards. One downside, however, is that they may be more prone to burst errors and FEC also adds latency, which may not be acceptable in certain applications. These considerations all influence the choice of PAM4 or NRZ.

EDN: Are any new innovations required for NRZ to keep carrying the load above 56-100 Gbps?
Eads: One tool being used today in high speed NRZ-based systems is a linear redriver, which is a type of analog continuous time linear equalizer (CTLE). Similarly, PCIe 4.0 and PCIe 5.0 will likely make extensive use of retimer chips. These devices act like a repeater and provide for a full PCIe channel (length) on both their upstream and downstream sides. This means that a motherboard which might only be able to accommodate 10 in. of trace at 32 GT/s and one connector could easily double that reach with the addition of a retimer (20 in. or more and up to two connectors in the signal past). The retimer is not free though; it costs both money and increases power consumption.

Yet another approach some engineers use are cables between chips in a system. Cables can be much better in terms of signal quality compared to PCB traces.

The other trick I’ve heard of for NRZ type systems is one where you add a third wire. One proprietary technology that uses this approach is called the Kandou bus. I don’t know a ton about it, but the company boasts very high signaling rates and uses NRZ signaling.


EDN: Under what extreme conditions would you say there is no choice but to move on from NRZ and how far is the industry from approaching those conditions?

Eads: From a standards perspective, a lot is decided by what the members of a particular consortium want to do. Some want to leverage their existing SERDES designs in other applications. The idea is that if something is working, try to step and repeat in a similar application space. Once again though, it starts with the channel. How much loss do you need to accommodate and at what frequency? At 32 GT/s NRZ, you look at the loss at 16 GHz. How many connectors do you need? How much loss do you budget for each connector? Can your market support the cost of better (lower loss) PCB material like Megtron 6 or Nelco 3030 or even Rogers?

I think NRZ has a lot of legs. One existence proof is to merely look at how far DDR has gone in terms of speed using single-ended signals. I never thought they’d get much beyond 1 GHz.

EDN: Do you think that PAM4 might be a mere fad?

Eads: No. I think there are good tools available today (PAM capable sampling scopes, real time scopes, bit-error ratio testers (BERTs) and arbitrary waveform generators (ARBs) that can be used to help prove out system transmitters and receivers. Test methods are improving and this all points to better and better interoperability over time. There are advantages to keeping the Nyquist frequency as low as possible while improving the data throughput. PAM4 can help to meet that challenge.

As always, Eads came prepared and ready to share what he knows. PAM4 can solve bandwidth problems but not without introducing problems of its own. Different applications in different signal integrity environments—PCB media, distance of signal propagation, noise, jitter, and crosstalk—are likely to call for different modulation schemes.

But one thing is for sure: if NRZ will work for you, you’d be crazy to switch to PAM4.

Ransom Stephens is a technologist, science writer, novelist, and Raiders fan who longs for Al Davis.

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