High frequency digital signals travel through a PCB's dielectric space, not the copper as you may think.
Part 3 of this series on PC board design for low EMI discussed partitioning and why that’s important to keep “noisy” signal fields from cross-coupling to “quiet” signal fields within the board’s dielectric space. In this article, I’ll provide more detail on partitioning. While the concept of partitioning is simple enough, real boards usually require a little more thought.
Partitioning is especially important when it comes to mixed-signal designs, such as a combination of analog and digital or wireless and digital. Many of my clients combine wireless (cellular, Wi-Fi, Bluetooth, and GPS) along with digital processing and sometimes analog (audio amplifiers or video, for example). For small mobile or IoT devices, the importance of adequately partitioning circuit functions becomes mandatory to eliminate digital switching currents from interfering with sensitive receivers.
This is a big problem for cellular wireless products that use the U.S. LTE bands in the range 700 MHz to 900 MHz and all the way up to GPS. EMI from digital processors, memory, and switch-mode power supply (SMPS) circuitry can produce harmonic energy out beyond commercial GPS frequencies (1,575.42 MHz). Today’s SMPS ICs are particularly nasty, due to their very fast edge speeds of less than 1 ns and high switching frequencies (of 1 MHz to 3 MHz, typically).
In part 3, I provided a conceptual diagram of the partitioning concept (Figure 1). By keeping all circuit functions separate, we avoid noisy signals from contaminating quiet signals. Simple in concept, but often difficult to achieve for real boards!
Figure 1 This conceptual diagram of partitioning shows separate circuit functions.
The problem with this conceptual drawing is that for real board designs, we need to consider a number of other issues. For example, the routing of clocks. We probably don’t want to run Ethernet and USB clocks all across our board. So, one important aspect would be to locate these functions closest to their associated connectors, as in Figure 2.
Figure 2 Here is a more practical partitioning of circuit functions.
In addition, it may make more sense to locate SMPS circuitry closer to what they power. It’s vital, though, to ensure all SMPS circuitry be run on the same layer and there must be an adjacent return plane. I’d still avoid locating SMPS circuitry too close to wireless modules or circuits – especially antennas.
In both Figures 1 and 2, power distribution is indicated by blue lines. Actually, the power distribution on real boards will likely be a combination of power planes (3.3 V is typical) and power polygons or routed wider traces for the other required power rails. This power distribution should also have an adjacent return plane that captures transient fields due to “ground bounce” switching currents.
Use of skin depth
Another method of partitioning is to use opposite sides of the same return plane to separate digital from RF or analog circuits. We can do this because skin effect at these high frequencies causes both digital and RF currents to travel along just the surface of the return plane and this layer is thin enough that the return currents don’t co-mingle. It’s like having two separate planes close together, but not touching, at these high frequencies. We can use Equation 1 to calculate the skin depth.
For example, at 10 MHz, the skin depth in copper is 0.8 mils and at 100 MHz, 0.26 mils (Note 1). Most of the signal current will be in this first skin depth. A one-ounce copper plane is 1.4 mils, so you can see that return signal currents flowing on each side of the plane won’t likely merge together in the middle; thus creating a theoretical “double-layer” of copper conducting plane (Figure 3).
Figure 3 Skin effect at high frequencies can theoretically separate a single plane into two separate, but close together, planes. Return currents from one will not contaminate return currents on the other.
Here is one stack-up idea that uses this concept and I’ve seen it used successfully by mobile device manufacturers (Figure 4). If we populate the top side of the board with all the RF/wireless components and the bottom side with the digital, power conversion, and control (while being careful to add return paths to all signals transitioning from top to bottom), theoretically, field energy from the one plane top won’t contaminate current in the other.
Figure 4 Partition a PCB by separating noisy circuits on the bottom side from contaminating sensitive circuits on the top side.
Note that we keep the main power distribution (usually 3.3 V) in the center of the stack-up. Very complex circuitry will likely require additional layers, depending on the number of circuit functions. One recent example was a mobile video platform with cellular, Wi-Fi, Bluetooth, digital video, and audio, and it used a 10-layer stack-up in order to separate functional blocks. Of course, there are many ways to accomplish this objective. Use Fig. 4 as one example.
I’m often asked my opinion on splitting analog and digital planes as a way to isolate digital noise currents from sensitive analog signals. Many A/D and D/A manufacturers suggest this technique in their application notes and even provide PC board layout directions (Figure 5).
Figure 5 A split-plane concept is often suggested for A/D or D/A circuits.
This is still an ongoing debate, and my opinion is that there are certain conditions that would warrant this technique. For most designs, if you use partitioning correctly, it will inherently provide isolation between noisy and sensitive circuit functions, even for A/D and D/A applications. For these latter cases, it’s just important to keep the analog traces away from the digital traces. Obviously, we don’t want to run traces of any kind across the gap.
The real issue when separating planes is that there will always be some high frequency voltage differential between the two and if the planes with their connecting I/O cables approach a significant fraction of a half-wavelength, it can be modelled as a dipole antenna and lead to radiated emissions and various immunity issues (Figure 6).
Figure 6 Two separate planes can induce a voltage potential between them and then radiate like a dipole antenna.
One of the few exceptions (and there are a few others, such as remote sensors) is the need for patient isolation for line-operated medical equipment. Figure 7 shows a typical grounding diagram where the analog probe processing is referenced to analog return, the digital processing circuitry is referenced to digital return, and the power supply is referenced to Earth. The digital and power returns would ideally be connected together at the power connector. This isolation device could be a specialized isolated coupler IC, an optical coupler, or several other similar devices.
Figure 7 This is a typical grounding configuration for a patient-connected monitor.
In practice, designing real PC boards for complex circuits is not for the faint of heart. There will always be trade-offs between partitioning of circuits, stack-up decisions, and routing of power and high frequency signals. However, if the basic design rules are followed; that is:
- Keep an adjacent return plane for both signal and power distribution layers
- Ensure a return path exists when transitioning through layers
- Partition different circuit functions as best you can
Then you’ll have a greater chance of keeping noisy signals away from quiet ones and the risk of radiated emissions, radiated immunity, ESD, and EFT compliance is much reduced.
I hope this four-part design series for low EMI has been helpful. Not too many instructors teach this concept yet and much of the design literature and “rules of thumb” are simply wrong.
Remember above all, high frequency digital signals travel within the dielectric space, not through the copper. Once you realize this, you can avoid the issue of noisy digital signals sharing the same dielectric space as low-level analog or RF signals and there will be a much greater chance of “doing it right the first time”!
I’d like to acknowledge the assistance and learnings from physicist Ralph Morrison, who realized years ago that fields must be considered when designing circuit boards; Rick Hartley, who teaches an excellent 2-day seminar on PC board design for low EMI and best signal integrity; and Daniel Beeker, senior applications engineer at NXP Semiconductor, who helped beat this concept into my head.
—Kenneth Wyatt is president and principal consultant of Wyatt Technical Services.
- Ott, Electromagnetic Compatibility Engineering (2nd Edition), Wiley, 2009, page 247 (Table 6-2).
- Ralph Morrison
- Rick Hartley, PCB2Day
- Daniel Beeker, NXP Semiconductor
- Effective PCB Design: Techniques To Improve Performance, Beeker
- Design PCBs for EMI, part 1: How signals move
- Design PCBs for EMI, part 2: Basic stack-up
- Design PCBs for EMI, part 3: Partitioning and routing
- 7 Tips for overcoming PCB EMI issues
- Manage EMI in PCB design: EMI sources and solutions
- Controlling Radiated EMI Through PCB Stack-up
- PCB design for low-EMI DC/DC converters