Here is a CPLD-based implementation of a stepper-motor driver that can also replace the driver in SAA1027- or UCN5804B-based designs.
Based on the Motorola (now Freescale) heavily used but obsolete SAA1042 stepper-motor-driver IC, this design idea describes a complex-programmable-logic-device (CPLD)-based implementation of a stepper-motor driver that can also replace the driver in SAA1027- or UCN5804B-based designs. The design uses only six macrocells of a Xilinx XC9536 CPLD and thus can implement multiple stepper-motor drivers in one small-capacity CPLD. The CPLD stepper-motor driver requires clock, direction, step-size, and reset inputs. The clock input accepts logic-level pulses and goes active on the pulse's positive edge. The direction, or CW/CCW (clockwise/counterclockwise), input determines the motor's rotational direction. Depending on the motor's electrical connections, holding this input at 0V normally produces CW rotation, and a logic-1 input produces CCW rotation. The step-size—that is, full- or half-step—input determines the motor's angular rotation for each clock pulse. Holding this input low commands the motor to execute a full step for each applied clock pulse, and a high input produces a half-step. A high level on the reset input puts the motor in a previously defined state and commands the CPLD to ignore any incoming clock pulses.
Figure: Emulating a dedicated stepper-motor controller, a programmable-logic device, IC1, applies stepper-motor signals to motor drivers IC2 and IC3.
The CPLD's outputs comprise A and A_n and B and B_n phases, each of which controls one of the motor's two coils through external power drivers IC2 and IC3, which operate at the motor's nominal voltage (figure). A pair of Schottky diodes at each driver's output protects the drivers' outputs during inductive-voltage transients induced by reversing the windings' currents. Using MOSFET drivers with internal diodes, such as Microchip's TC4424A dual driver, may eliminate the requirement for external diodes.
Table: Driver outputs for each machine state.
The CPLD's program comprises an eight-state Moore finite-state machine that corresponds to the motor's eight half-step states. The table shows the driver's outputs for each machine state. In full-step state mode, the state machine executes only Step 0, Step 2, Step 4, and Step 6. At each clock pulse's rising edge, the machine state changes from Step(n) to Step(n+1) if CW/CCW is high or from Step(n) to Step(n–1) if CW/CCW is low. You can download a generic VHDL implementation of the stepper-motor-driver firmware. Although written for an XC9536 CPLD, the code is also suitable for any CPLD or FPGA target device.
This article is a Design Idea selected for re-publication by the editors. It was first published on March 1, 2007 in EDN.com.