For more than a decade, wideband satellite payload communication systems were built with data converters that used a low-voltage differential signaling (LVDS) data interface to a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). This combination has been able to keep up with the expanding sample rates, and the corresponding sampled bandwidths, during that time frame but hit an upper boundary when data converter sample rates reached approximately 1.6 G samples per second (SPS) per converter. The new JESD204B chip-to-chip data interface standard is now gaining the chip support to enable a breakthrough to the next level.

The problem designers are facing is that interfacing 1.6 GSPS of 12-bit data using LVDS requires an 800-MHz double-data-rate (DDR) interface with 12 LVDS data lines – largely considered the practical upper limit for reliably closing timing with an LVDS interface to FPGAs. In most cases, a demultiplexed-by-2 data stream using two 800-MSPS buses (400-MHz DDR) between the analog-to-digital converter (ADC) and the FPGA was needed to relax the timing requirement. This scheme came at the cost of twice as many lanes and twice the board routing area. It also required tightly matching the layout of all differential pairs in the board routing, which led to an inefficient and bloated board layout. Saving board space is very important on a space payload, where every ounce is costly to launch, and every square millimeter of board space is valued at a premium.

Meanwhile, data converter core speeds have now exceeded the capabilities of LVDS interface rates, and the commercial data converter industry has largely moved to the Joint Electron Device Engineering Council JESD204B serial interface standard. In order to give space-payload radio-frequency (RF) transceivers a boost in bandwidth beyond where LVDS can take them, space industry component manufacturers will need to use this new standard interface.

What is JESD204B?

JESD204B uses an 8-bit/10-bit encoded data interface to serialize data chip to chip over differential lanes. This enables a breakthrough to the next level of signal bandwidths that wideband communications designers are looking for beyond LVDS because the upper limit of the written JESD204B specification is a 12.5-Gbps lane rate. Designers can use this lane rate to aggregate many converters into one lane or can employ a multilane configuration to carry large amounts of data from one data converter to and from an FPGA.

Because JESD204B does not require matched trace lengths between link pairs, designers can optimize board routing to save board space and avoid the extra routing LVDS usually requires in order to match the shortest straight-line traces to the longest paths. The JESD204B specification has elastic buffering built in to accommodate for variances in trace lengths. For systems that require synchronized receivers, JESD204B allows for a simple method of using a distributed low-frequency SYSREF signal to achieve multi-device synchronization.

Completing the JESD204B ecosystem

Major data converter suppliers now offer many catalog (non-space-grade) products that use the JESD204B standard, and catalog FPGA vendors have produced the JESD204B intellectual property necessary to keep up with (and in most cases exceed) the speed capability of current data converters. Unfortunately, space-grade FPGAs have been limited in their SerDes input/output (I/O) speeds, which has slowed the transition from LVDS to JESD204B in space applications because the overall system bandwidth could not improve what LVDS offered. The highest capability in SerDes speed up until now has been <5 Gbps, found in both Microchip RTG4 and Xilinx Virtex-5QV series space-grade FPGAs.

If the industry had attempted to go much beyond 1.6 GSPS using LVDS in space-grade components, it would have required over 100 pairs of matched-length differential connections between the data converter and the FPGA. But now, with JESD204B, the amount of data that devices such as the Texas Instruments ADC12DJ3200QML-SP ADC have been able to push using only eight differential connections has reached 6.4 GSPS. The device achieves 6.4 GSPS of 12-bit data output by running the eight JESD204B SerDes lanes at 12.8 Gbps each. It is now conceivable to continue to increase data converter sampling rates for space applications, by either expanding to more differential connections, speeding up the link, or both. This will enable a substantial increase in signal bandwidths and data rates transferred over the RF link to and from satellites.

Figure 1 shows an example of SerDes processing under the standard. The analog channel represents the board’s high-speed digital data signal between devices. It is called the analog channel here because a 12.8-Gbps SerDes link is treated like an analog or RF signal in the board design and for impedance matching. If the link is not given this attention, the eye diagram at the receiving end will not be open and aligned for proper capture. The JESD204B transmitter is the output data from the ADC after it is serialized, and the JESD204B receiver is the input to the FPGA (labeled the “logic device” in Figure 1) that will need deserializing.

JESD204B data processingFigure 1 This simplified JESD204B interface diagram shows the digital link from an ADC to an FPGA as an analog channel to reflect the need for board layout to treat the signal as analog.

Moving data communications in space applications to JESD204B, however, will require not only space-grade data converters but also space-grade FPGAs that can work together with them to provide the next level of signal bandwidth. These devices must continue to provide the latch-up and total ionizing dose (TID) capabilities required for space missions.

Fortunately, such devices will soon be available. To support the complete JESD204B ecosystem, multiple FPGA suppliers are announcing that they will release space-grade FPGAs with faster SerDes speeds and support for JESD204B. Xilinx, for instance, has announced that it will transition a version of the Kintex UltraScale class of FPGA to space-grade in the XQRKU060, with 32 SerDes transceivers capable of 12.5-Gbps lane rates. Figure 2 is a picture of the ADC12DJ3200QML-SP board connected to the Alpha Data board that contains the Xilinx XQRKU060 for a 12.5-Gbps JESD204B interoperability test.

JESD204B development boardFigure 2 The ADC12DJ3200EVMCVAL (red) connected to the Alpha Data space development kit (green) show that space-grade components for JESD204B are becoming available to designers.

Other vendors are following suit. NanoXplore has announced that they will offer a space-grade FPGA with 6.25-Gbps SerDes in the NG-LARGE and 12.5-Gbps SerDes in the NG-ULTRA. Microchip has announced that it will support 24 SerDes transceivers at 10-Gbps in their space grade variant of the RT PolarFire FPGA.

The FPGA-ADC system will not work without a proper clocking solution to tie everything together synchronously. Devices such as the Texas Instruments LMX2615-SP, a space-grade clocking chip, can now provide this capability up to clock frequencies of 15 GHz.

JESD204B radiation characteristics

Space-payload designers will need to understand the characteristics of devices that use JESD204B when they encounter heavy ions. Although the probability is low, the serial link may be interrupted by heavy ion strikes in orbit. Texas Instruments published the first single-event effect characterization of a JESD204B interface at the 2019 Nuclear and Space Radiation Effects Conference. A summary of the results for the ADC12DJ3200QML-SP are:

  • The serial link always self-recovers automatically from a heavy ion strike.
  • The average recovery time of the serial link is 1.3 µs, with a worst-case measurement of 11 µs.

Keep in mind, though, that these are the results for just one example device. Each integrated circuit will have different results and thus will require careful characterization under the beam to determine the overall bit error rate based on component choices, shielding environment, and operational orbit. A JESD204B-compliant receiver with proper error handling will be necessary to achieve quick recovery if heavy ions interrupt the link.

Now that data converters, FPGAs and clocking devices are available that support the JESD204B interface in space-grade components, an ecosystem is established for applying the standard in space. Designers can now start handling the next generation of system bandwidth in wideband satellite communication and radar payloads.

Philip Pratt


Philip Pratt is the marketing lead on the high-speed data converter team at Texas Instruments in Dallas for aerospace and defense application customers worldwide.






Additional resources:

  1. Review Texas Instruments’ JESD204B Overview and JESD204B Physical Layer (PHY) High Speed Data Converter Training slides.
  2. Read EDN’s coverage of the Microchip RT PolarFire FPGA.
  3. Read Rajan Bedi’s overviews of Xilinx and NanoXplore FPGAs: Kintex UltraScale FPGAs for space applications and BRAVE new ITAR/EAR-free space-grade FPGAs.