These new models will enable parasitic extraction tools to accurately capture silicon variation that impacts timing and reliability analysis.
Synopsys has released extensions to its open-source licensed Interconnect Technology Format (ITF), which enables additional modelling of complex parasitic effects between device structures and interconnect layers at the advanced 10nm and 7nm process nodes. These new models will enable parasitic extraction tools to accurately capture silicon variation that impacts timing and reliability analysis, according to the company.
Synopsys collaborated with members of the Interconnect Modelling Technical Advisory Board (IMTAB), an IEEE-ISTO Federation Member Program, to refine and ratify these new extensions. They are available in the Synopsys ITF version 2016 through an open-source licence.
"Dealing with increasing variation and complexity at 10nm and below process nodes requires continuous modelling innovation as well as providing usable standards to facilitate easier adoption," said Bari Biswas, vice president of Engineering for extraction solutions at Synopsys and chair of IMTAB. "Working together with IMTAB members and leading foundries, Synopsys has taken another big step forward by enriching the ITF format with refreshed and extended models to support effects of advanced multi-colour patterning and 3D FinFET devices, while ensuring the simplicity to enable efficient enablement and deployment."
The new IMTAB-ratified extensions to ITF include:
- Gate-to-diffusion device parasitic modelling enhancements for required accuracy at 10nm/7nm
- Colour-aware thickness variation extension for triple and quad colour patterning
- Density-aware thickness variation improvement for enhanced modelling of CMP effects
- Silicon coverage-based via resistance for improved accuracy based on silicon dimensions
- Dielectric fill modelling for accurate coupling capacitance extraction of ultra-low dielectrics