Xilinx’s RT-ZU19EG will be more advanced compared to the company’s current space-grade FPGA offerings, delivering 10x improvement in performance and capability.
At the ESA and NASA FPGA workshops held last year, Xilinx revealed that its next space-grade PLD would be the RT-ZU19EG part from the new 16nm FinFET UltraScale+ MPSoC family. They noted that the RT-ZU19EG will be offered in the same ceramic package as the V5QV QMLY FPGA, but will contain a distinct hardened version of the commercial ZU19EG die, where RT denotes radiation tolerant.
Recent NSREC, RADECS, and MAPLD conferences have presented work on the radiation hardness of ultra deep-submicron FinFET transistors. Total-dose damage depends on where charge builds up in the isolation oxides and how this affects active areas. The change in geometry between 3D transistors and planar ones results in a different response to TID: some bulk FinFETs have shown a sensitivity to charge build-up in the sidewalls with threshold shifts, while narrow-fin SOI transistors are intrinsically resistant.
The creation of an SEE depends on the critical charge required to upset a device and its charge collection capability. Both of these depend on device geometry, operating voltages and circuit topology, with some FinFETs requiring more time to remove radiation-induced carriers.
Ordinarily, using conventional 2D transistors, a 16nm process with low core voltage (from 0.72V to 0.9V) will have good intrinsic total-dose and latch-up tolerance. However, the increased logic density of ultra deep-submicron semiconductors means that a radiation strike can result in multi-bit upsets.
In terms of raw performance, the RT-ZU19EG will be many generations ahead of the V4 and V5QV space-grade FPGAs currently offered by Xilinx as listed below. Its speed and range of logic resources greatly exceeds the capability of all existing SRAM, antifuse, and flash-based qualified PLDs.
Figure 1: The table shows a comparison of Xilinx space-grade FPGAs.
However, as I demonstrate on my FPGA course, big does not mean best and a large ultra deep-submicron PLD may not always be the most efficient (e.g., power consumption, PDN, physical footprint, or cost) digital solution when a small amount of digital control or processing is required locally within a spacecraft. Saying that, the 3D structure of a FinFET transistor significantly limits short-channel leakage through its body and together with lower supply voltages, offers real potential to optimise performance together with reduced power consumption. For example, a 16 nm FinFET process can offer a 50 per cent increase in performance or a 50 per cent decrease in power dissipation compared to 28 nm.
Xilinx's UltraScale+ MPSoC family is a heterogeneous processing platform combining a processing system (PS) with field-programmable logic (PL) in the same device as shown in Figure 2.
For the ZU19EG, the PS contains three major processing units:
- A quad-core, 64-bit, ARM v8 Cortex-A53 application processing unit (APU)
- A dual-core, 32-bit, ARM v7 Cortex-R5 real-time processing unit (RPU)
- A Mali-400 graphics processing unit (GPU)
These processing elements connect via a central switch to multiplexed I/O (MIO) peripherals, various memory, and high-speed serial link interfaces as shown in Figure 2.
The PS and PL have independent and isolated supplies providing four distinct power domains:
- PS full-power domain (FPD)
- PS low-power domain (LPD)
- PL power domain (PLPD)
- Battery-powered domain (BPD)
Depending on the speed grade and required temperature range, the core voltage of the PL can vary from 0.72V to 0.9V, allowing you to trade performance with power consumption. At a hardware level, the number of voltage regulators can be consolidated to a minimum of four or five based on your specific system priorities.
Figure 2: Zynq UltraScale+ MPSoC top-level block diagram (Source: Xilinx)
I have started designing-in various UltraScale+ parts for ground and space-segment clients, and have created a Matlab script which reads the pin-lists provided by Xilinx and produces files for each bank in a format that automatically generates fractured circuit symbols for schematic entry for use with the Mentor Graphics' xDxDesigner/Expedition PCB flow. I have also coded an ActiveX script which accesses pins within the design and magically commons the different PS/PL power rails as well as all the GNDs (that's symbol creation and graphical connection of almost 40 per cent of the device's pins in one minute to exploit your time-to-market needs!). I/O Designer already supports the UltraScale+ parts optimising and unravelling I/O assignments to minimise routing effort.
From the XPE spreadsheet, overall chip estimates for the commercial ZU2EG to the ZU19EG range from 1.5W to 22W, respectively. The latter is similar to the V5QV but delivering a 10x improvement in performance and capability. To meet time-to-market needs and reduce hardware development costs, a scalable power distribution architecture for the UltraScale+ parts has been created which allows you to select different regulators (COTS for space or fully qualified) based on the choice of MPSoC. Similarly, various configuration memory options also exist. These concepts exploit the design reuse feature provided by the xDxDesigner/Expedition PCB flow, which allows certified schematic and layout blocks to be imported into different projects.
To increase productivity, the xDxDesigner/Expedition PCB flow also provides a variant manager to allow you to quickly select the desired manufacturing build, e.g. test components used by MPSoC during prototyping can be removed from the flight hardware with the software automatically generating the appropriate schematic, BOM, and assembly drawing. If you would like to learn more about designing-in UltraScale+ parts, I compare the UltraScale+ RT-ZU19EG with all other space-grade PLDs (and some COTS) on my FPGA course. Powering and clocking different MPSoC devices are also discussed.
Just like the commercial world, FinFET technology offers a lot of potential for the space industry and I look forward to seeing its radiation tolerance and long-term reliability de-risked for future satellite and spacecraft applications. First samples of the pin-compatible commercial ZU19EG will become available in the second half of this year with the RT-ZU19EG to be released in 2018. It's a bit early to say if Xilinx will de-rate the specification of the qualified part, however, I'm excited by the very high-throughput mission opportunities which RT-ZU19EG will enable and look forward to sharing my hardware and software design-in experiences with you!
Later this year, I will be presenting a webinar on the RT-ZU19EG as well as publishing a series of articles on designing-in the device for satellite avionics implementing spacecraft IP.