The BiCS FLASH with TSV technology targets storage applications that require low latency, high bandwidth and high IOPS/Watt.
Toshiba Memory Corp. is developing a BiCS FLASH 3D flash memory by combining through-silicon via technology with 3-bit-per-cell (triple-level cell, TLC) technology.
Devices fabricated with TSV technology have vertical electrodes and vias that pass through silicon dies to provide connections. This architecture enables high-speed data input and output while reducing power consumption, according to Toshiba. The architecture is also used in Toshiba’s 2D NAND Flash memory.
By combining a 48-layer 3D flash process and TSV technology, product programming bandwidth is increased while achieving low power consumption, Toshiba said. The power efficiency of a single package is approximately twice that of the same generation BiCS FLASH memory fabricated with wire-bonding technology, Toshiba added. The TSV BiCS FLASH technology also enables a 1TB device with a 16-die stacked architecture in a single package.
Shipments of prototypes for development purposes started in June. Product samples are scheduled for release in the second half of this year.