The Stratix GX device includes a built-in serialiser/deserialiser circuit that supports high speed LVDS interfaces at data rates of up to 1.6Gbps.
Linear Technology has shown how to interface an LTM9011 8-channel, simultaneous sampling 14bit analog-to-digital converter (ADC) with high speed serial low voltage differential signaling (LVDS) to Altera Stratix IV FPGAs using the dedicated I/O functions of the FPGA family.
The LTM9011 is a high speed, octal ADC with a serial LVDS interface. Each channel output can be configured in 2bit (2 lanes) mode or 1bit (1 lane) mode. While, the Stratix IV GX FPGA development board is a hardware platform for developing and prototyping low power, high performance and logic-intensive designs. The board contains a Stratix IV GX FPGA EP4SGX230KF40 (BGA 1517 pins) and offers a wide range of peripherals and interfaces to facilitate the development.
The DC1884A demo board is connected to the FPGA board through a high density flexible cable, SAMTEC SCF-156146-02-MA, adapting the SAMTEC SEAF (FMC) connector of the demo board to a high speed mezzanine card (HSMC) connector (J2) of the FPGA board. This connection carries 20 high speed LVDS lines: 16 lines for data OUT#A and OUT#B, two lines for data clock DCOA and DCOB and two lines for the frame signals FRA and FRB, which are generated by the LTM9011 on the DC1884A demo board. The LTM9011 requires an external clock source with ultralow jitter as a sample clock (ENC) and eight analog signal inputs.
The Stratix GX device includes a built-in serialiser/deserialiser (SERDES) circuit that supports high speed LVDS interfaces at data rates of up to 1.6Gbps. Pin assignment is important in Stratix IV FPGA LVDS applications because only some of the I/O blocks support full LVDS features and only some of the PLLs support these I/Os. The Stratix IV device family supports LVDS on both row and column I/O banks.
In conclusion, the 1.6Gbps SERDES features of the Altera Stratix IV GX FPGA suits the LTM9011 and other serial LVDS output analog to digital converters. The architecture of the ALTLVDS megafunction allows the implementation of ultra-high speed LVDS receivers under very simple timing constraints.
The LVDS receivers can properly capture high speed serial data streams without input buffer skew adjustment since the DPA circuitry tracks any dynamic phase variations between the clock and data.
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