On-board mass memory requirements for the new space age

Article By : Rajan Bedi

NAND flash technology offers a potential non-volatile solution to enable future on-board mass memory needs for Earth-observation

Earth-observation analytics can be used to provide satellite-based insights to address societal needs such as food sustainability, monitoring climate change, deforestation, disaster management, smart cities, imaging to locate natural resources such as oil and gas, as well as continuous, real-time monitoring of critical assets in remote areas. The latest predictions for this market are valued at $8 billion by 2026.

Figure 1 This is an illustration of ESA’s Fluorescence Explorer Earth-observation mission.

To exploit the lucrative market opportunity, industry and governments are looking for more and more applications that would benefit from space technology, while operators are trying to differentiate by offering better services, like ultra-high-resolution streaming video.

Real-time video or acquiring higher-resolution images impacts on-board mass memory requirements. Advances in fast, high-capacity space-grade memory have lagged behind the options available to our commercial cousins and radiation-hard, plastic 16 Gb DDR3 SDRAM has only just become available, offering system frequencies up to 667 MHz.

The next generation of Earth-observation applications will require payloads with Tbs of on-board storage to process the acquired remote-sensing data. As an example, realising 1 Tb of mass storage would require 64 DDR3 chips with a total memory cost of $650,000, significantly increasing the size, complexity, and power consumption of the payload. For most OEMs and operators, DDR3 is simply not a viable option for this on-board requirement.

NAND flash is a higher-density memory technology that is ubiquitous in the commercial world; how many of you own Tb flash drives? These offer non-volatile storage by exploiting floating-gate transistors, are organised, and function differently than conventional semiconductor static and dynamic memory. Table 1 compares DDR3 with NAND flash when implementing 1 Tb of on-board storage.

Table 1 Realising 1 Tb of on-board storage

DDR3 16 Gb x 16 NAND 256 Gb x 16
Number of devices 64 4
Minimum real estate
152,320 16,796
Power dissipation
17 W/17 W 13.2 mW/5.2 W
Approximate cost ($) 650,000 30,000
Storage rate,
16 bit bus (Mbytes/s)
2667 100
Total byte writes (TBW) Unlimited 7530 Tbs

Due to yield-related issues, NAND flash is fabricated with a known number of erroneous blocks. Furthermore, this technology degrades with time due to repeated use of the memory cells and there is a specified reliability limit regarding the total number of bytes that can be written (TBW) over the lifetime of devices. NAND flash contains intrinsic error-correction spare bits, is intended for linear, contiguous storage, and can be considered a solid-state hard drive. A controller is required to manage its interface, the location of bad blocks, and additional deterioration over the lifetime of a mission.

NAND flash memory is organised into pages, blocks, planes, and logical units (LUNs), as illustrated below. A target is the amount of memory accessed by a chip enable signal and can contain one or more die, which is the minimum that can independently execute commands and report status. According to the Open Nand Flash Interface (ONFI) specification, a die is referred to as a LUN.

Each page contains 8640 bytes, comprising 8192 bytes of data and 448 for error correction and wear-levelling, i.e. ensuring blocks are exercised uniformly.

NAND flash memory organisationFigure 2 This diagram shows the organisation of NAND flash memory.

To reduce pin count, data, commands, and addresses are multiplexed onto the same pins and are received by I/O control circuits. Commands are latched into a register and transferred to logic for generating internal signals to manage device operations. The addresses are latched and sent to a row/column decoder to select the desired location within the NAND flash memory array.

LUN functional block diagramFigure 3 This is a LUN functional block diagram.

All operations start with an instruction cycle by placing a command on DQx, driving CE# low, CLE high, and clocked by a rising edge on WE#. This is followed by an additional instruction or one or more data cycles.

The NAND flash memory array is programmed and read using page-based operations and is erased using block-based instructions. In normal page mode, the data and cache registers act as one. During cache operations, the data and cache registers operate independently to increase data throughput; you can access data from the cache register while array data is being transferred to the data register.

synchronous command latch cycleFigure 4 Here is the synchronous command latch cycle.

Comparatively, current space-grade NAND flash operates in slow asynchronous mode only with a maximum I/O speed of 50 MHz, and the RE#/WE# control input transitioning read and write transfers respectively when a device is enabled. The maximum time to write one page (8640 bytes) of data to the cache is 173 µs, and 560 µs to transfer this from the cache to the memory array. The subsequent time to write one byte is 64.8 ns and this must occur within the clock period of 1/50 MHz = 20 ns. Commercial-grade NAND flash offers faster synchronous operation.

To increase sustained array (page program) bandwidth, within a device, multi-plane mode allows both planes to be written simultaneously, halving the above time to 32.4 ns. Each plane contains independent cache and data registers and as shown in Figure 2, there are two die per chip enable allowing multi-plane, multi-LUN mode, permitting multiple die to be accessed at the same time, e.g. by using two die, the write (page program) time of 64.8 ns can be reduced to 64.8/4 = 17.4 ns. By simultaneously interleaving data to four planes on two die, you can fit the time required to write one byte within the 20 ns clock period so the array page programming time is now faster than the I/O time. The data will not be stored contiguously, but spread over two die, and a memory controller within a FPGA/ASIC must manage this process.

As an example, Data Device Corporation (DDC) offers space-grade NAND flash available from 32 to 256 Gb, so only four chips are required to realise 1 Tb of storage. Figure 2 shows that a 256 Gb chip comprises four 64 Gb targets, each containing two 32 Gb die. Dual data busses are available to allow simultaneous access to four LUNs. Procurement options range from engineering samples for use at +25°C, industrial grade from -40 to +85°C, as well as class A, K, and H devices from -55 to +125°C. RAD-PAK shielding is also available to increase total-dose tolerance to > 100 kRad(Si) in most orbits and parts are offered in ceramic hermetic packages. DDC performs die lot specific total-dose testing on every die lot and performs single-event effect (SEE) testing on a die revision basis. Radiation reports are available upon request and DDC can reconcile customers’ specific hardness requirements by analyses to guarantee that devices meet your required mission needs.

A clock period of 20 ns to write one byte results in a I/O rate of 50 Mbytes/s: as each DDC chip contains two 8-bit I/O busses, this can be increased to 100 Mbytes/s, which is equivalent to 800 Mbps. Four chips results in a data rate of 3.2 Gbps.

DDC has confirmed that typically there are few if any bad blocks at beginning of life (BOL) but the number increases up to 80 at EOL (end of life). This equates to 5.4 Gb of unusable storage per chip or a total of 21.5 Gb when using four devices. The resultant total capacity at EOL would be 1.001 Tb and you are told which blocks are faulty at BOL.

The 256 Gb NAND flash chip has a specified lifetime endurance of 60,000 cycles denoting the number of times the device can be written or erased. A total of 1.001 Tb * 60,000 equals 60,240 Tbs, which is equivalent to a TBW of 7530 Tb. The resulting mission duration can be calculated from your storage needs: if you need to write 1 Tb of data per year, the memory will operate for 7.5 years.

DDC 256Gb NAND flash chipFigure 5 This space-grade, 256 Gb NAND flash chip features a x16 wide bus.

An IBIS model is available and as the packages are leaded devices, you have to create your own PCB footprints. I would like to see schematic symbols offered in a neutral CAD format like BXL to expedite time-to-market needs!

I would like to see hi-rel suppliers offer faster and larger products for space-grade memory. While space-grade DDR4 is on its way, NAND flash remains the only technology capable of providing Tbs of on-board mass storage economically and at low power to exploit market opportunities. The I/O speed of radiation-hardened NAND flash needs to be improved to align with future avionics needs as well as the latest FPGAs, and IP is required to control this interface and manage memory degradation and errors over the lifetime of a mission. Conveniently, the DDC parts support both 3V3 and 1V8 I/O, the latter being very useful when connecting to ultra-deep-submicron banks, as well as reducing dynamic power. Both faster, synchronous higher-density NAND flash and DDR4 are on their roadmap.

Until next month, the first person to tell me how a floating-gate transistor exhibits non-volatility will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Giulia from Naples, Italy, the first to answer the riddle from my previous post.

— Dr. Rajan Bedi is the CEO and founder of Spacechips

Related articles:

Leave a comment