Optimize mixed-signal Circuit/PCB design using noise modeling, part 1

Article By : Mark Wagner

An in-depth tour of ways to model and reduce noise in analog, digital, and mixed circuits & PCBs.

This article will help you move advanced mixed-signal & wireless designs away from the design-build-test (-hope) paradigm, towards getting it right by design, the first time, with confidence.

Articles on noise sources and noise topology related to op-amps, resistors, digital gates, and other devices are numerous, but missing are quantitative ways to begin approximating effects on mixed-signal systems. Also missing are means for managing & analyzing noise from power rails and separate grounds: e.g., what do you do with the PSRR curve of an op-amp?

To make decisions on grounding and shielding, it is useful to model a system as fundamental circuit elements with noise sources and parasitic coupling elements. Current flow observations and simple voltage dividers provide useful data based on science rather than simple rules of thumb. The complexity of this approach can be managed by using SPICE if the number of nodes grows beyond a “back of the envelope” calculation. These techniques are useful in both analog and digital realms, as the problem of moving a signal from one point to another – with fidelity – is the same. The differentiators are frequency, signal amplitudes, and input & output impedances. Here’s what’s ahead:

Part 1

  1. Components described by fundamental circuit elements (RLC)
  2. Noise sources, obvious and no so obvious
  3. DC Power bus as a noise source
  4. Earth Ground Noise sources
  5. Quantified Noise Source Amplitudes
  6. Putting it all together

Part 2

  1. Specific Example of Isolated RS-485 Links
  2. Specific Example of a microcontroller analog input / Using PSRR Curve
  3. Specific Example of a generic singled ended input (analog or digital)
  4. Summary
  5. Appendices:
  • Limitations and scope of this approach
  • Kirchhoff’s Voltage and Current Laws
  • Fundamental assumptions for controlling EMI


Components described by fundamental circuit elements (RLC)

Generally the goal is to understand how the environment (off-board equipment) or nearby section of circuit will interfere with an analog or digital input. In order to analyze that, we can create a simplified system model with a V or I source, and various circuit elements as lumped parameter models (RLC) to do a nodal analysis. The simplest coupling model is electrostatic, where the primary coupling element is a capacitor. Modeling electromagnetic interference can be done, but is much more complex given the fact that you likely will have the equivalent of a single turn transformer with loose coupling, and an unknown resonant frequency.

In cases like that, it is recommended such conditions be modeled at the input of the device in question with a voltage source at the aggressor frequency, and the amplitude estimated by the V/m signal strength on the conductor in question. The cable inductance will likely dominate the output impedance of this “source”, so an inductor of its estimated value should be placed in series with this voltage source. Optimize the input impedance of your circuit to reject that frequency the best you can within space/cost constraints while maintaining the required signal bandwidth.

Input structures can be modeled by what is stated in a datasheet. Typical components used would be RLC, but if RF rectification is a concern (for DC-sensitive inputs), then add a diode – such as for internal ESD suppression – to the power rails. If you do this, you may have to also enter voltage sources so their effect only occurs at a specific voltage levels (adding a DC voltage source in series with the diodes). Typical IC input structures for logic inputs have approximately 10pf capacitance to signal ground, but the datasheet should be consulted to see if it is specified. If the input impedance is not stated, you will have to estimate it from the specified input voltage and leakage or bias current.

Keep in mind that the goal here is not a 1% solution, but order of magnitude optimization. Estimating an input resistance with a variation of 100K or 200K will not matter much as our target is to have the external bias network present an input impedance of less than 500 ohms, if possible, to lower susceptibility. Use of IBIS models for digital devices is another approach to get more fidelity of input/output modeling and will be covered in my next article.

Figure 1  Simplified input circuit


Devices such as transformers and DC-DC converters (which sometimes have transformers) will have parasitic capacitance from input to output (for isolated converters), and that value of capacitance can be valuable in determining if additional measures are required (like ferrites) to control common mode currents. Again, if these parameters are not specified, your choices are to estimate based on similar parts, or attempt to measure a sample.

These models also help in understanding isolated circuits, and what can happen when leakage paths are not controlled, and are exclusively determined by manufacturing, environmental, or part variation. While I have seen some designs which show adding capacitance across a transformer isolated boundary, noise modeling will generally indicate that is not beneficial. Allowing more RF current to flow from one stage to another may radiate more. The approach is to observe a potential leak path, and try to limit current flow, and/or try to shunt it to the reference ground, connected faraday cage, or nearby chassis.

Shielded systems will make use of the shield-to-conductor, or conductor-conductor capacitance specifications to build your model. Shield resistance end-to-end is usually modeled as 0 ohms, but this may be adjusted if other values in the circuit are below 10 ohms.

Figure 2  AC model for DC-DC converter


Noise sources: Obvious, and not so obvious

Noise sources are sometimes the most difficult to determine in this analysis. Obvious ones are a circuit node driven by a clock signal on a Circuit Card Assembly (CCA) or a cable. Because of the harmonics, it is usually best to model a noise source emulating this element as 5-10× the fundamental frequency to account for the harmonics to perform a worst case analysis. Data lines can be modeled as well, but the choice of the modeled frequency may be less obvious. The characteristic of interest is the signaling rate[1], or the number of state changes per unit time.

If a 115kbaud RS-422 data line is modeled, the frequency would be actually be 57.5 kHz (square wave), because there is no state change between bits if adjacent bits are “1”. So modeling the highest signaling rate would require an alternating bit pattern (010101) which would result in 1/2 the baud rate. We then must account for harmonics as a square wave has significant harmonic content at least out to 5× the fundamental. Modeling more complex modulation schemes may require a different approach, but for a first order approximation, a basic signal could be assumed. You could increase the frequency slightly; say 50%, to provide a derating factor to the calculation and account for some unknowns or precision in this computation.

Noise sources associated with AC Lines can be very strong in some applications. Line frequency is typically 50 or 60Hz. Military applications may be 400Hz. Because higher currents are involved, magnetic coupling can be a problem and circuit coupling can be visualized that way. This translates many times to a common mode problem, so that topology should be considered to see if your circuit is sensitive to that. Protecting against line frequency coupling issues is very difficult; and as such, noise is best controlled by single point grounds and large isolation impedances. This can be modeled to see the numeric response, and/or help visualize best design choices for connectivity. Noise riding on AC lines can be modeled by inserting a transformer/voltage source in series with the connection.

Figure 3  AC line noise


DC power bus as a noise source

We discussed the obvious sources (clocks), but more common aggressors are the power rails as they are connected to all your ICs. The noise amplitude can be estimated based on the voltage rail used, or the type of device (Table 1). Noise sources should be below the targets in the table, though the lower, the better. Noise’s effect will vary depending on the DC input levels, and how we deal with it will depend on the application, some of which will accept the occasional wrong input; but some will fail with greater consequences.

If you have measured specific numbers, use those values. The maximum signal frequency to model on a DC power line can be estimated from the minimum rise time of the chips involved, as mentioned previously, using BW = 0.35/rise time as a first-order approximation. Devices switching at these speeds put disturbances on the power lines at these frequencies. Analog power rails, by their very design, should be 50mV or less (again the amount may vary on the voltage of the power rail). Measurement of historical circuits within your company can improve the accuracy of the simulations.

Another assumption made is the author’s preference – for using values as P-P noise. You may prefer to use RMS if you are heavily averaging signals. However, if you design for P-P noise resulting in only a few bits on an A/D input, the need for heavy digital signal processing is reduced.

There is an important distinction between digital and analog ICs. Analog ICs generally are designed to reject noise on their power rails, with this rejection dropping off as frequency increases. Digital devices with totem pole outputs have minimal or no rejection at all of any noise on the power bus. This is important distinction as signals transition through the threshold voltage (switching point). Excessive high frequency noise may produce multiple transitions, glitches, or jitter on your output when rise times are too slow.

Adding capacitance may slow the slew rate down too much risking latch up, or severe jitter. Always observe the maximum rise time for a signal if you choose this approach. It is usually best to clean up your power rails first and ensure that the noise is within the values listed in Table 1.


Earth-ground noise sources

Earth-ground noise is very difficult to quantify since it varies greatly depending on the application and length of cable runs. In order to start a path to modeling this type of problem, it helps to visualize RFI current paths to optimize shielding, ground connections, and ferrite placement. Earth ground connections within an instrument cabinet are not the concern here, although it can be an issue for circuits sensitive to signal levels below 10mV. Here we are considering ground connections a few feet or more apart. This includes two devices that may communicate with each other, but are plugged into different power strips. Connections less than 10m apart will likely not have much of a low frequency voltage difference (f < 120Hz), but may have significant high frequency noise.

Beyond that distance, large AC and DC voltage potentials can appear requiring isolation which can be modeled. Some of these can be destructive (V>50V), so the standard caution to watch for ground loops with very distant connections apply. Be careful of rules of thumb, as shorter runs (<15m) may require shield grounding at both ends to address magnetic coupling concerns.

A rough estimate for this type of noise model can start with amplitudes of 1-2 volts P-P at frequencies up to 100 MHz in series with a voltage source at 50/60Hz. The goal here is to provide as much immunity as can be afforded given cost and space, rather than a specific amount of attenuation unless you have already made field measurements of the phenomenon to gauge the voltage differential and spectral content.

Figure 4  Earth-ground noise modeling


Quantified noise source amplitudes

In order to quickly answer the question of “is a noise source going to affect my circuit?”, we need a means to estimate what noise source amplitudes would be acceptable for most systems. Table 1 provides a conservative guideline for noise amplitudes based on the input threshold band of the device in the circuit [4].

These noise targets are generally used as guides for what to expect on a given power rail. Because logic devices don’t provide any power supply noise rejection, that power rail noise will end up on your signal. While assuming a static logic signal at a marginal voltage for a given logic level, noise added to this voltage will risk an uncommanded change in its logic state (positive or negative pulses). Keeping the noise amplitude as a small percentage of a device’s input range will make a more reliable system. The noise level on power buses should be a design target, not just something you accept as a result of first build.

Analog devices are more application-specific in terms of noise requirements. Some of these devices have power supply rejection, shown above.  Comparators need to have noise levels less than their circuit dependent hysteresis to avoid glitches. Voltage reference noise amplitudes should be managed based on the effective resolution of the A/D subsystem, or other downstream devices. Voltage references may also specify a PSRR, which will aid in determining what your voltage rail noise target should be to get an acceptable output noise level.

Table 1:



















































25% of hysteresis band

Hysteresis is determined by external components


Voltage Reference (such as 2.5V)



Depends on expected S/N ratio and # bits


Putting it all together

Now that we have a methodology of modeling the circuit elements, we need to choose which ones will be dominant and just model those to keep the size of the model manageable. This usually means visualizing a current path, which will come with some practice, and/or measuring the performance of your prototypes in their intended application. The analysis technique used will vary depending on the threat.

Single clocks may have a singular frequency, and thus a transient analysis in PSpice may be desired. Broadband noise sources such as CCA bus noise or earth ground noise may be handled by a frequency sweep and AC analysis. The load that this attenuation is measured across is usually your circuit input node. To make a decision of acceptability, you will need a desired signal-to-noise ratio as a goal. In the case of LVTTL or RS422, the signal amplitude is defined, and from this analysis, you will now have a peak-to-peak measurement of predicted noise, so a direct comparison is possible, hence the reason for the preference of modeling noise in P-P format.

If the above process is followed, you have greatly improved your chances of building a robust circuit. Approximations were made in this analysis. So, what if you still experience issues with a physical unit? By setting up the simulations you already have an idea of how to inject signals into a real circuit on the bench.

Electrostatic noise injection is fairly straight forward. You can connect a signal generator to a suspected node with a capacitor (just watch the loading on your generator). When in doubt, SPICE again can provide insight into what you might expect from your generator with 50Ω output impedance. Inductive injection is a bit more difficult, but possible. For guidance here, see the article from Douglas C. Smith [2].

Use your simulation to understand the loading on the generator, especially when dealing with higher voltages, to ensure you don’t damage your test equipment, and use the oscilloscope to verify results and agreement with the model. Standard 10:1 probes are usually adequate, but understand their characteristics in modeling: 10MΩ in parallel with 5-10 pf (check the datasheet).

In Part 2, we’ll run through some examples, as well as limitations and assumptions of this modelling approach.


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