This final article in the series explores RTD system optimization, selection of external components, and how to evaluation the final RTD system.
In the first article in this three-part series on RTD, we covered temperature measurement challenges, RTD types, different configurations, and the RTD configuration circuit. In the second article, we outlined the three different RTD configurations: 2-wire, 3-wire, and 4-wire. In this final article in the series, we’ll explore RTD system optimization, selection of external components, and how to evaluation the final RTD system.
RTD System Optimization
Looking at system designer issues, there are different challenges involved in designing and optimizing RTD application solutions. Challenge one is the sensor selection and connection diagram that were discussed in the previous sections. Challenge two is the measurement configuration, which includes the ADC configuration, setting the excitation current, setting the gain, and selecting the external components while ensuring system optimization and operating within the ADC specification. And lastly, the most critical issue is how to achieve the target performance and what are the error sources that contribute to the overall system error.
Luckily, there is a new RTD_Configurator_and_Error_Budget_Calculator that offers a hands-on solution in designing and optimizing RTD measurement systems from concept to prototyping.
The tool is designed around the AD7124-4/AD7124-8. It allows the customer to adjust settings such as excitation current, gain, and external components (Figure 1). It indicates out-of-bound conditions to ensure that the final solution is within the specifications of the ADC.
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Figure 1. RTD configurator. (Source: Analog Devices)
Selection of Excitation Current, Gain, and External Components
Ideally, we tend to select higher magnitudes of excitation current to generate a much higher output voltage and maximize the ADC input range. However, since the sensor is resistive, the designer must also ensure the power dissipation or self-heating effects of a large value of excitation current will not affect the measurement results. A system designer may select a high excitation current. However, to minimize self-heating, the excitation current needs to be turned off between measurements. The designer needs to consider the timing implications for the system. An alternative approach is to select a lower excitation current that minimizes self-heating. Timing is now minimized, but the designer needs to determine if system performance is affected. All scenarios can be tested via the RTD_Configurator_and_Error_Budget_Calculator. The tool allows the user to balance the selection of excitation current, gain, and external components to ensure that the analog input voltage is being optimized along with tuning the ADC gain and speed to give better resolution and better system performance, which means lower noise and lower offset error.
To understand the resulting filter profile or to get a deeper understanding of the timing of the conversions, the VirtualEval online tool provides this detail.
The ADC input and reference inputs of a sigma-delta ADC are both continuously sampled by a switched capacitor front end. For the RTD systems being discussed, the reference input is also driven by an external reference resistor. An external RC filter is recommended on the analog input of a sigma-delta ADC for antialiasing purposes. For EMC purposes, a system designer may use large R and C values both on the analog input and the reference input. Large RC values can cause gain errors in measurements as the front-end circuitry does not have sufficient time to settle between sampling instants. Buffering the analog and reference inputs prevents these gain errors and allows unlimited R and C values to be used.
For the AD7124-4/AD7124-8, when using an internal gain greater than 1, the analog input buffers are automatically enabled and since the PGA is placed in front of the input buffers, as the PGA is rail to rail, the analog input is also rail to rail. However, in the case of the reference buffers or when using the ADC at a gain of 1 with analog input buffers enabled, it is necessary to ensure that the headroom required for correct operation is met.
Signals from Pt100s are low level. They are in the order of hundreds of mV. For optimum performance, an ADC with wide dynamic range can be used. Alternatively, a gain stage can be used to amplify the signal before it is applied to the ADC. The AD7124-4/AD7124-8 support gains from 1 to 128, thus allowing an optimized design for a wide range of excitation currents. The multiple allowed options of PGA gain allow the designer to trade off excitation current value vs. gain, external components, and performance. The RTD configurator tool indicates whether the new excitation current values can be used with the selected RTD sensor. Suitable values for the precision reference resistor and the reference headroom resistor are also suggested. Note that the tool ensures the ADC is used within specification—it displays possible gains that will support the configuration. The AD7124 excitation currents have an output compliance; that is, the voltage on the pin providing the excitation current needs some headroom from AVDD. The tool will also ensure that this compliance specification is met.
The RTD tool allows the system designer to guarantee a system that is within the operating limits of the ADC and the RTD sensor. The accuracy of the external components such as the reference resistor and its contribution to the system error will be discussed later.
Filtering Options (Analog and Digital 50 Hz/60 Hz Rejection)
As discussed earlier, an antialiasing filter is recommended with sigma-delta converters. As the embedded filter is digital, the frequency response is reflected around the sampling frequency. Antialiasing filtering is required to adequately attenuate any interference at the modulator frequency and at any multiples of this frequency. Since sigma-delta converters oversample the analog input, the design of the antialiasing filter is greatly simplified and a simple single-pole RC filter is all that is required.
When the final system is used in the field, dealing with noise or interference from the environment in which the system is operating can be quite challenging, especially in application spaces such as industrial automation, instrumentation, process control, or power control, where being tolerant to noise and at the same time not being noisy to your neighboring components is required. Noise, transients, or other interference sources can impact the system accuracy and resolution. Interferences can also occur when systems are powered from the mains supply. Main power supply frequencies are generated at 50 Hz and its multiples in Europe, and 60 Hz and its multiples in the U.S. Thus, when designing an RTD system, a filtering circuit with 50 Hz/60 Hz rejection must be considered. Many system designers want to design a universal system that rejects both 50 Hz and 60 Hz simultaneously.
Most of the lower bandwidth ADCs, including AD7124-4/AD7124-8, offer a variety of digital filtering options that can be programmed to set notches at 50 Hz/60 Hz. The filter option selected has an effect on the output data rate, settling time, and the 50 Hz and 60 Hz rejection. When multiple channels are enabled, a settling time is required to generate a conversion every time the channel is switched; thus, selecting a filter type with longer settling time (that is, sinc4 or sinc3) will lower the overall throughput rate. In this case, a postfilter or FIR filter is useful to provide reasonable simultaneous 50 Hz/60 Hz rejection at lower settling times and thus increasing the throughput rate.
The current consumption or power budget allocation of the system is highly dependent on the end application. The AD7124-4/AD7124-8 contain three power modes that allow trade-off between performance, speed, and power. For any portable or remote application, low power components and configurations must be used, and for some industrial automation applications, the complete system is powered from the 4 mA to 20 mA loop so that a current budget of only 4 mA maximum is allowed. For this type of application, the devices can be programmed in mid or low power mode. The speed is much lower, but the ADC still gives high performance. If the application is process control, which is powered from the mains supply, a much higher current consumption is allowed, so the device can be programmed in full power mode and this system can achieve a much higher output data rate and increased performance.
Error Sources and Calibration Options
After knowing the required system configuration, the next step is to estimate the errors associated with the ADC and the system errors. These help system designers to understand if the front end and ADC configuration will meet the overall target accuracy and performance. The RTD_Configurator_and_Error_Budget_Calculator allows the user to modify the system configuration for optimum performance. For example, Figure 2 shows a summary of all the errors. The system error pie chart indicates that the external reference resistor’s initial accuracy and its temperature coefficient are the main error contributors to the overall system error. Thus, it is important to consider using an external reference resistor with higher accuracy and a better temperature coefficient.
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Figure 2. RTD error sources calculator. (Source: Analog Devices)
The error due to the ADC is not the most significant error contributor to the overall system error. However, the error contribution from the ADC can be reduced further using the AD7124-4/AD7124-8’s internal calibration modes. An internal calibration is recommended upon power-up or software initialization to remove the ADC gain and offset errors. Please note that these calibrations will not remove errors created by the external circuitry. However, the ADC can also support system calibrations so that the system offset and gain error can be minimized, but this may add additional cost and may not be required for most applications.
For any harsh environment or for applications where safety is a priority, diagnostics are becoming part of the industry requirements. The embedded diagnostics in the AD7124-4/AD7124-8 reduce the need for external components to implement diagnostics, resulting in a smaller, simplified time and cost savings solution.
These diagnostics lead to a more robust solution. The failure modes, effects, and diagnostic analysis (FMEDA) of a typical 3-wire RTD application have shown a safe failure fraction (SFF) greater than 90% according to IEC 61508.
RTD System Evaluation
Figure 3 shows some measured data from circuit note CN-0383. This measured data was captured with the AD7124-4/AD7124-8 evaluation board, which includes demo modes for 2-, 3-, and 4-wire RTDs, and calculated the corresponding degree Celsius value. The results show that a 2-wire RTD implementation gives an error closer to the lower limit of the error boundary, while the 3-wire or 4-wire RTD implementation has an overall error that is well within the allowed limit. The higher error in the 2-wire measurement is due to the lead resistance errors described earlier.
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Figure 3. A 2-/3-/4-wire RTD temperature accuracy measurement postfilter in low power mode at 25 SPS. (Source: Analog Devices)
What these examples show is that following the above RTD guidelines will lead to a high accuracy, high performance design when used in conjunction with ADI’s lower bandwidth sigma-delta ADCs such as the AD7124-4/AD7124-8. The circuit note (CN-0383) will also serve as a reference design that helps the system designer get to prototyping quickly. The evaluation board allows the user to evaluate the system performance wherein each of the sample configuration demo modes can be used. Going forward, firmware for the different RTD configurations can be easily developed using ADI generated sample code available from the AD7124-4/AD7124-8 product pages.
ADCs, which use a sigma-delta architecture such as from the AD7124-4/AD7124-8, are suitable for RTD measurement applications since they address concerns such as 50 Hz/60 Hz rejection, as well as wide common-mode range on the analog and possibly the reference inputs. They are also highly integrated, containing all the functions needed for an RTD system design. In addition, they provide enhanced features such as calibration capability and embedded diagnostics. This level of integration, along with the complete system collateral or ecosystem will simplify the overall system design, cost, and design cycle from concept to prototyping.
To ease the system designers’ journey, the RTD_Configurator_and_Error_Budget_Calculator tool along with the online tool VirtualEval, the evaluation board hardware and software, and CN-0383 can be used to address the different challenges, such as connectivity concerns and the overall error budget, and bring the users to the next level of their design.
This article has demonstrated designing an RTD temperature measurement system is a challenging, multistep process. It requires making choices in terms of the different sensor configurations, ADC selection, and optimizations and how those decisions impact overall system performance. The ADI RTD_Configurator_and_Error_Budget_Calculator tool, along with the online tool VirtualEval, the evaluation board hardware and software, and CN-0383 streamline the process by addressing connectivity and overall error budget concerns.
This article was originally published on Embedded.
Jellenie Rodriguez is an applications engineer at Analog Devices within the Precision Converter Technology Group. Her focus is on precision sigma-delta ADCs for DC measurements. She joined ADI in 2012 and graduated from San Sebastian College-Recoletos de Cavite with a bachelor’s degree in electronics engineering in 2011. She can be reached at firstname.lastname@example.org.
Mary McCarthy is an applications engineer at Analog Devices. She joined ADI in 1991 and works in the Linear and Precision Technology Applications Group in Cork, Ireland, focusing on precision sigma-delta converters. Mary graduated with a bachelor’s degree in electronic and electrical engineering from University College Cork in 1991. She can be reached at email@example.com.