Advanced packaging technologies improve performance of heterogeneously integrated IPs on package and help scale bandwidth between die-to-die links on package.
In the past few years, there have been a number of announcements involving advanced packaging architectures for semiconductor devices. These architectures offer product designers tremendous flexibility in being able to heterogeneously integrate different IPs optimized on different silicon processes on package and hence offer significant performance enhancements.
Recent interest in advanced packaging is driven by the need for increased on-package bandwidth, the need to integrate diverse IPs from multiple foundries, and the need for improved yield resiliency. Organic packages are excellent mainstream platforms for heterogeneous integration, offering space transformation in compact form factors and increasingly improved—power efficient and high bandwidth—physical on-package interconnects (Figure 1).
Figure 1 The Intel Agilex FPGA provides an example of on-package heterogeneous integration. Source: Intel
One of the goals of advanced packaging is to develop increasingly dense lateral and vertical interconnects such that the die-to-die links created with these interconnects have minimal power loss and latency while ensuring signal integrity. Essentially, the focus is to create on-package interconnects that approach monolithic interconnect performance, and the composite device created on the package behaves as a virtual monolithic entity.
2D and 3D architectures
The on-package interconnects, and more broadly the package architectures with these interconnects, can be classified as 2D in the x-y plane of the package and 3D (Figure 2).
Figure 2 The interconnect nomenclature for 2D and 3D architectures. Source: Electronics Packaging Society, IEEE
The 2D architecture is defined as an architecture where two or more active silicon devices are placed side-by-side on a package and are interconnected on the package. If the interconnect is “enhanced”—has higher interconnect density than mainstream organic packages and is accomplished using an organic medium—the architecture is further sub-categorized as a 2D organic (2DO) architecture. Similarly, if the enhanced architecture uses an inorganic medium—a silicon, glass, or ceramic interposer or bridge—the architecture is further sub-categorized as a 2DS architecture.
The 3D architecture is defined as an architecture where two or more active silicon devices are stacked and interconnected without the agency of the package. The phrase “interconnected without the agency of the package” in this definition simply means the interconnects between the active silicon do not pass through the package and hence their design and performance does not directly depend on the package architecture.
Physical interconnect density can be captured by two key metrics (Figure 3). A linear density represents the number of wires escaping the die edge for lateral die-to-die interconnects and an areal density characterizes the number of bumps used to form vertical connections.
Figure 3 Linear and areal interconnect density can be captured by these two key metrics. Source: Intel
Figure 4 and Figure 5 describe the envelopes for the linear and areal densities for different packaging technologies. As both figures indicate, a wide range of interconnect densities are possible with different interconnect architectures. In general, technologies that use silicon back-end wiring have the highest wiring densities because they offer thinner and more closely-spaced wires (Figure 4).
Figure 4 This graph shows linear interconnect density envelopes for different advanced package architectures. Source: Intel
These technologies enable parallel, wide, and slow die-to-die links and they require careful attention to link design to account for signal-integrity concerns with increasing wiring densities. As the bump pitch shrinks, the areal bump density increases proportionally to the reciprocal of the square of the bump pitch (Figure 5).
Figure 5 This graph shows areal interconnect density as a function of bump pitch and architecture. Source: Intel
A vast majority of the areal die-to-die and die-to-package interconnects today use solder to form the joints. As bump pitch shrinks, there will be a transition away from solder to using Cu-Cu interconnects (at ~20-25 μm) to enable continued interconnect density scaling. Hence, there is a focus in the industry to increase the technology envelope of Cu-Cu interconnects.
A common underlying reason for interconnect density scaling is the need to increase bandwidth for on-package die-to-die links. The rate of bandwidth scaling can be used to define an interconnect scaling roadmap. According to the Heterogeneous Integration Roadmap 2019 Edition, the interconnect technology scaling roadmap enables generational doubling of link bandwidth.
Figure 6 shows some examples of advanced packaging architectures for heterogeneous integration.
Figure 6 Some advanced package architectures offer increased partitioning opportunities and scaling in all three dimensions. Source: Intel
Collaboration between package and system designers
As advanced-packaging technologies evolve, they will provide increased on-package performance through heterogeneous integration, which enables increasingly higher performance systems. This system performance can be better realized by strengthening collaborative partnerships between package and system designers.
Some examples of how collaborative partnerships will help maximize system performance are listed below:
In conclusion, a number of advanced packaging technologies are available today to improve performance of heterogeneously-integrated IPs on package. There is a focus on scaling interconnect densities in these technologies to help scale bandwidth between die-to-die links on package and to drive performance. Closer collaborations between package and system designers to optimize package system integration will help maximize system performance.
This article was originally published on EDN.
Ravi Mahajan, an Intel fellow, is technology development co-director for Assembly and Testing Future Technology at Intel.