PAM4 signaling for high-speed DRAM

Article By : Richard Quinnell

Micron Technology has brought PAM4 signaling to high-speed DRAM in a release that may well be the dawn of the multi-level logic era.

For decades we have seen a relentless demand for more in our industry: more processing, more memory, more data bandwidth. This has led memory systems to adopt ever-widening buss widths and ever-increasing clocking speeds. Finally, however, a new option is becoming practical – increasing the number of bits per pin.

Traditional memory interfaces have used the same kinds of signaling that standard logic uses, a non-return to zero (NRZ) binary with two signal levels conveying one bit. Networking and other high-speed buses like 56G Ethernet, however, began switching to a multi-level signal some years ago. Their four-level pulse amplitude modulation (PAM4) signaling scheme encodes two bits per signal line and a number of transceivers are currently available that support this scheme.

The advantages of PAM4 are obvious. The scheme doubles the data rate for a given clock speed compared to NRZ or, put another way, halves the clock speed for a given data rate. If you need higher bandwidth, you can get it. If you don’t need the bandwidth, the lower clock frequency translates to lower power consumption in CMOS logic as well as reduced radiated EMI concerns in system designs.

There are drawbacks to using this coding scheme, however, which have until now restricted its use. There is, of course, the added cost and complexity of the extra logic needed to decode the two-bits-per-line signal for handling by traditional one-bit-per-line processors. More importantly, though, is the reduction in noise margin that four-level signaling incurs.

As Figure 1 shows, the eye diagram of NRZ signaling is much more open than for PAM4 signaling for a given noise level. In quantitative terms, the SNR for PAM4 is about -9.54 dB compared to NRZ. This reduction forces developers to exercise much tighter control of circuit board traces and makes chip design more critical. Taken together with the extra logic cost, these considerations have so far precluded use of PAM4 in processing design and limited its adoption to bulk data transfers.

Micron illustration of PAM4 signaling comparisonFigure 1 PAM4 signaling transfers data at half the clock speed of NRZ, at the cost of reduced noise margins. (Source: Micron Technology)

The situation has recently changed. To address the high memory bandwidth needs of graphics and artificial intelligence (AI) processing, Micron Technology has brought PAM4 signaling to high-speed DRAM with its GDDR6X DRAM. Working in conjunction with Nvidia, which has developed a compatible memory controller for its RTX 30 series GPUs, Micron has been able to deliver system memory bandwidth up to one terabit per second (Tb/s) in a volume production chip.

This was no mean feat. Ralf Ebert, director of the graphics memory business for Micron Technology, indicated in a press conference that the company had been researching the technology since 2006, and in product development for nearly three years before releasing the GDDR6X. They developed some 45 patents on PAM4 signaling along the way.

The concept is simple. To convert an incoming PAM4 signal to a pair of NRZ bits, for instance, what you need is multiple threshold detectors operating in parallel (Figure 2). In the Micron device, these detectors offer programmable thresholds, allowing devices to be tuned to their specific operating environment for maximum reliability.

4-level signaling receiverFigure 2 Multiple threshold sensors are needed to convert a PAM4 signal back into traditional NRZ logic. (Source: Micron GDDR6X datasheet)

The devil, of course, is in the details. Developers considering the use of PAM4 signaling in their system memory will need to exercise greater care than usual in designing and fabricating their boards. Further, although the four levels in PAM4 use Gray code assignments so that adjacent levels only differ by one bit, developers may also need to incorporate error correction coding (ECC) to compensate for the reduced SNR of PAM4 signaling. And testing the interface presents its own set of challenges.

Still, the release of a memory device and corresponding controller that works with multi-level signaling rather than binary and can be produced in volume is significant. It means that the era of binary logic may be starting to ebb. It’s early days yet, of course, and where cost is a critical factor it may be decades yet before binary slips from mainstream use. This release may well be the dawn of the multi-level logic era.

Micron has not yet submitted the memory interface to JEDEC to become an industry-wide standard. Still, it is an open standard, allowing other developers to consider developing systems by working with Micron to adopt the technology. The goal is to leverage the graphics market’s volume demand to push down prices, encouraging other applications to make the switch to PAM4 memory. It will be interesting to see how quickly the transition occurs.

This article was originally published on EDN.

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