Parasitic extraction at advanced nodes
Article By : Christopher Clee, Mentor Graphics
Solving speed/accuracy trade-offs at advanced nodes remains a challenge.
Some parasitic extraction constraints in semiconductor design evolve continuously between process generations. For example, the increasing dominance of interconnect vs. gate delay, and the similar dominance of sidewall capacitance vs. plate capacitance for interconnect on lower metal layers. Each of these constraints emerged several generations ago, and while the problems they address may have become more acute with each successive new process geometry, tried-and-tested modeling solutions have been part of our design flows for many years. But increasingly, sudden transitions are becoming the norm—consider the introduction of multi-patterning and finFET transistors in recent generations of nanometer processes. New extraction capabilities must be developed to address these new technologies and the impacts they create on designs.
Another factor affecting extraction requirements is the expanding use of established nodes for new and emerging product markets, such as the Internet of Things, automotive electronics, and medical devices. To differentiate their established nodes to a broader number of analog, mixed-signal, and radio frequency (RF) semiconductor designers, foundries are continually improving the electrical characteristics of already well-established process technologies such as 40 nm, 55 nm, and even larger. These incremental improvements create their own discontinuities—for example, when physical intellectual property (IP) is redesigned at these nodes. The design industry is experiencing an emerging dominance of three-dimensional line-end effects inside cells that challenge modeling assumptions made by traditional parasitic extraction tools.
Extraction technology today
Most electronic design automation (EDA) approaches to parasitic extraction use two distinct extraction methods. A rule-based approach measures the dimensions of the wires in the design and the separation (distance) from neighboring wires, then plugs these values into an internal model to calculate the parasitic values. To generalize the parasitic model so it can apply to any foundry or process, rule-based extraction tools use a set of multi-dimensional tables or equations derived from the process specifications to generate the correct variables for the tools’ internal parasitic equations. Generally speaking, rule-based extraction offers fast processing with reasonable accuracy when interconnect delay is the dominant effect.
Field solvers calculate the strength of electromagnetic field lines by solving Maxwell’s equations [1]. This approach is compute-intensive, meaning it is also time-intensive. However, field solvers generally return the most accurate results, not the least because field solvers can not only handle complicated three-dimensional geometries, but they’re also not restricted to some pre-conceived model of the parasitic effects that may or may not arise in any given situation. The field solver provides the necessary accuracy around three-dimensional structures (like finFETs and local interconnect) that alternate approaches like pattern matching (which uses a limited set of pre-characterized devices) cannot. Accordingly, field solvers are typically used by foundries to generate “golden” reference results that are used to validate the accuracy of other extraction techniques.
Figure 1 illustrates a highly-simplified overview of the flow that rule-based extraction tools use, in contrast to the flow that field solvers use.
Figure 1 Rule-based vs. field solver flows
Extraction technology innovation
Both rule-based and field solver extraction are necessary techniques for any advanced node design. The challenge for design companies is to develop an extraction flow that optimizes and integrates the best aspects of both approaches, to reduce the designer’s workload and minimize extraction runtimes. However, until now, using different extraction approaches meant independently accessing the different extraction engines, which not only increases the time required to complete parasitic extraction, but also makes it hard to reconcile the results, increasing the time it takes to get to design closure.
Some EDA companies have introduced extraction tools designed for use on advanced nodes that make it easier to combine the accuracy of a field solver engine with the fast performance of a table-based extraction engine by incorporating both engines in a single platform. This technology blend enables these tools to be highly accurate around devices, while also providing extremely fast extraction for designs containing many millions of nets. This hybrid approach to extraction effectively accelerates the performance of the field solver by automatically applying the field solver around devices and on lower metal layers, while using a fast, accurate, and scalable rule-based approach to deliver the accuracy and performance required for the many millions of nets on the multiple diverse routing layers typical of nanometer processes.
Solving the problem of burgeoning design size also means taking a unique approach to multi-threading (processing different nets independently using different threads or CPUs). For greatest efficiency, a hybrid extraction tool must be completely thread-safe, so there are no unwanted interactions or dependencies between threads. With order-dependent effects eliminated, the tool can process nets in an arbitrary order, with no effect on the extracted values. This approach provides a highly-scalable solution and ensures the consistency of results from run to run, regardless of the number of CPUs used or the compute platform that you choose.
Additionally, this technique avoids the inherent problems that existing partitioning approaches have with scalability and repeatability. For example, if you cut a design into windows, the number of windows you create depends on the number of CPUs you allocate. You must also add a “halo” to each window, meaning the extraction tool must effectively extract multiple times in these regions and stitch the results back together, which introduces run-to-run variations. Also, as you ramp up the number of windows, the area of the halo regions rises relative to the area of the windows, limiting scalability. Net-based multi-threading removes this limitation altogether. Results are deterministic, so you get the same answers regardless of the orientation of the design, number of CPUs, or any other variables that don’t impact the process or the design geometry.
To further reduce the verification engineer’s workload, hybrid extraction tools typically support some means of stitching field solver and net-based extraction results together for analysis, because nets usually have segments on both lower and upper metal layers. Lastly, for accurate signoff, these tools must provide all needed functionality, including multi-patterning support and simultaneous multi-corner processing (which generates multiple netlists—one per process or temperature corner—from a single run).
Summary
For advanced nanometer processes, features such as FinFET transistors, and processes like multi-patterning, require a significant increase in the accuracy of parasitic extraction for simulation and analysis to verify the performance of a physical design. At the same time, market demand and tight delivery schedules mean design teams require an extraction tool that is faster, more accurate, and more flexible than previous generations. New extraction tools must be able to quickly and accurately generate field solver-accurate results inside rule-based timeframes, while providing all designers, whether digital, custom, analog, or RF, with the extraction accuracy and performance they need.
Chris Clee is a Calibre verification Product Marketing Manager at Mentor Graphics.
References
[1] “Maxwell’s Equations,” Engineering and Technology History Wiki
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- Device-level extraction becomes an issue for SoC designers
- Efficient parasitic extraction techniques for full-chip verification
- Parasitic extraction in the age of double-patterning
