EMI from DC-DC converters has long plagued designers of wireless and IoT devices; here are answers to pressing questions on PCB design to reduce it.
Self-generated EMI from DC-DC converters has long plagued designers of wireless and IoT devices. The broadband harmonic content often extends up through 1.5 GHz, which includes most wireless protocols, cellular LTE, and GPS/GNSS bands.
I’ve written several articles and presented webinars on how to reduce self-generated EMI for wireless and IoT devices and one of the key methods to resolve self-generated EMI is through proper PCB design. Some articles are mentioned in the references below, and I recently presented a lengthy webinar on the subject. If you missed the presentation, the recorded version is located here. The webinar elicited several questions on PCB design and reducing EMI from DC-DC converters and you’ll find my answers below.
Q: When is it OK to reference the power plane with a circuit trace?
This is a common question and arises from the use of the typical four- and six-layer board designs where power and ground return planes are usually quite separated (Figure 1). If you understand that high frequency (>100 kHz) signals are really electromagnetic waves, whose return currents are typically referenced to digital ground return, then you’ll better understand why referencing to the power plane is a bad idea. Those return currents need to find a way back “somehow” to digital return and the path they take may create EMI. In my opinion, non-critical signals (low frequency, control signals, etc.) may be referenced to power, if and only if, the power and return planes are very closely coupled and well bypassed with decoupling capacitors. This is NOT generally the case for the typical four- and six-layer board stack-ups. In most cases, running high frequency digital signals referenced to the power plane is HIGH RISK for EMI. I would suggest referring to my four-part series on designing boards for low EMI.
Q: Would “ground pours” help isolate noisy signals?
The very best way to isolate “noisy” signals is through proper PCB stack-up; that is all high frequency (>100 kHz) digital signals’ traces should be adjacent to a solid return plane. This will bound the electromagnetic wave. Breaks in the return plane can cause an increase of 15 to 20 dB in EMI (see my video demo on the web site in the References). According to Dr. Eric Bogatin, ground pours more often don’t actually help and can also be detrimental, depending on the board design, because they can appear as “breaks” in the return plane in some cases. I’d refer you to his web site for more information on PCB design and the topic of ground pours.
Q: When running a clock trace from the top to the bottom of a board, how important is it to add vias nearby for the return current?
It depends; the usual answer to many EMC questions! If the power and return planes are located close together (2-3 mils, max) and there are adequate decoupling capacitors located around the board, then it’s not as important to add a nearby via for the return current path. However, for critical traces like clocks, I’d add one or more in order to ensure a tight bound for the electromagnetic wave. I’d again refer you to my series on PCB design for low EMI.
Q: What effect does rise and fall times have on EMI and what sort of percentage should rise and fall be of pulse width?
Dr. Eric Bogatin has some excellent discussion on this topic in his book, Signal and Power Integrity Simplified, 3rd edition (see the recommended book list below). Briefly, you can use the equation BW = 0.35/RT, where BW (bandwidth) is in GHz and RT (rise time at 10-90%) is in ns. So, for a rise time of 1 ns, the bandwidth is about 0.35 * 1 GHz, or 350 MHz. The pulse width affects the amplitude of the harmonics. As it decreases, the overall amplitude decreases, as well. As the pulse width decreases, there will be a point where the rise and fall times will start to appear as a rounded pulse (given fixed RT/FT), so there’s a point where the nice square pulse shape starts to fall apart. I’m not sure of any general rule for percentage RT versus pulse width.
Q: Electrons only travel at 1 cm per second?
This question has to do with my explanation on how digital signals propagate in PCBs. Most of us were taught (or at least it was implied) that signals were really electron flow in copper wires or traces and that the electrons moved at near light speed. While this is true for DC circuits, electrons DO NOT travel at near light speed, because they are too tightly bound within the copper molecules. At high frequencies (>100 kHz), digital signals are really electromagnetic waves propagating through the dielectric layer between the copper trace and return plane. Between DC and 100 kHz, there’s a transition region where signals convert from pure DC currents to electromagnetic waves.
Figure 2 A cross-section of a microstrip over ground return plane is a physical depiction of a digital signal in the form of an electromagnetic wave traveling within the dielectric space between the trace and return plane.
This electromagnetic propagation model is comprised of two elements; the propagating wave itself, which travels at about half light speed in the dielectric (assuming FR4 dielectric) and a combination of conduction current, which IS electron flow in copper molecules, and displacement current (“through” the dielectric) (Figure 2). This conduction current is what you’d measure with an ammeter, but the electrons are only traveling about 1 cm/sec. I’ve found this physical model of digital signal propagation is not generally taught in most fields and waves textbooks. However, there are two references I’d recommend: Signal and Power Integrity Simplified, 3rd edition, by Dr. Eric Bogatin (pages 245 to 252) and Electromagnetics Explained – A Handbook for Wireless/RF, EMC, and High-Speed Electronics, by Ron Schmitt (pages 33-34, 84-86 and 96-98). Also see my series on PCB design for low EMI.
Q: Are the power modules having integrated inductors better for low EMI?
Yes, because the input and output loop areas are minimized. An example is Linear Technology’s “μModule” system on a chip (SoC). See Figure 3 and the Analog Devices page on μModule buck-boost regulators.
Figure 3 This example of a DC-DC converter from Linear Technology shows the integrated inductor (or transformer in this case), Cin and Cout all integrated into an SoC. This design minimizes the noisy current loops, reducing EMI. Source: Linear Technology
Q: Do we need cut outs down to the bottom underneath the switch node plane to reduce electric field coupling?
That’s an excellent question! Obviously, we want to minimize the trace area of the switch node (SW) trace to the inductor to reduce the coupling to this point that can be switching up to 42-V square waves in this example and can produce intense E-fields (Figure 4).
Figure 4 Here is a typical DC-DC buck converter, showing the switch node (SW) and output inductor. The debate centers around whether to cut away the return plane either around the SW node or inductor, or both. Source: Linear Technology
Several years ago, I felt cutting away the return plane in the area of the switch node (SW) was important for reducing capacitive coupling until I really started studying how digital (or power switching, in this case) worked from a physics point of view. While I now believe strongly that the return plane should be maintained as a solid plane under all portions of DC-DC converters, your argument cannot be discounted completely and may depend on the exact situation.
Well-known experts in EMC and PCB design (Dr. Todd Hubing, Rick Hartley, and Daniel Beeker) maintain the return plane should be solid. On the other hand, SI and PDN experts I know (Steve Sandler, for one) are thinking along your lines. Currently, I’ve initiated a study amongst myself, Steve Sandler, and Todd Hubing where we’ll investigate this question. Steve has agreed to build several circuit boards and test for signal and power integrity and I’ll be measuring the radiated and conducted emissions. It should be interesting and may end up as a technical paper. Currently, my opinion on a solid return plane stands until proven otherwise.
Q: With the absorber material we see that EMI is attenuated. But isn’t the stuff then put somewhere else – unpredictable – inside the circuits instead of leaving to the outside?
The radiated emissions from ICs or circuit traces actually get absorbed and converted to heat in the lossy ferrite material.
Q: Are series ferrite beads on DC-DC converter inputs and outputs a good idea?
Having come from an RF design background, this was pretty common practice for RF circuits – and I still believe that technique may be used successfully. In recent years, as I’ve studied power integrity, I’ve come to change my mind. For good power distribution network (PDN) performance, you don’t want any series impedances in the PDN. This was illustrated clearly by the late Steve Weir in his PowerCon presentation, as well as recent textbooks by Dr. Eric Bogatin and Larry Smith in their book, Principles of Power Integrity for PDN Design Simplified. If you do choose to try these in input or output filters, be sure to add an extra bulk capacitor (4.7 to 27 μF ceramic) between the ferrite bead and digital switching converter IC. I still don’t recommend adding these.
Q: Should DC-DC converters be placed on the bottom-side of the PCB and sensitive analog circuits on the top-side?
Yes, that’s a great idea and one that some of my clients have used successfully. Typically, the RF section is built on the top layer and all the digital processing and control are located on the bottom layer. It’s very important to have at least one solid ground return plane in the middle and you need to be careful how any critical (that is high-frequency) signals are routed between top and bottom. It’s important to ensure a continuous path for return currents along with the signal via.
Q: Example of excellent DC-DC converter PCB design?
All I can suggest at this time is to reduce the loop areas of both the Cin and Cout (plus switching inductor) by locating these components very close to the DC-DC converter IC and to maintain isolation between the input circuit and output circuits. Locate all the associated components on either the top or bottom side of the board and ensure a solid return plane adjacent.
Q: You referred to sharing Cin and Cout ground pin. Can you revisit this topic again?
When Cin (the noisy loop for buck converters) and Cout (the noisy loop for boost converters) share the same current return path to ground, noise can couple via that common impedance return path and contaminate the “quiet” side (of whichever buck/boost topology is being used). Figure 5 shows a good example where Cin and Cout are connected to the same point. Note that it’s not just TI that suggest these inadvertently poor layout recommendations, but ALL device manufacturers do at times. You need to be able to trace out the main current loops and ensure primary and secondary circuits are separated well apart from each other.
Figure 5 This example of poor circuit layout for TI’s LMR33630 shows Cin and Cout sharing the same ground return path. This common impedance coupling will couple noise currents of this buck converter to the output voltage rail. Source: Texas Instruments
Q: What is the optimal way to isolate Cin and Cout ground references on a DC-DC converter?
This is related to the question above. The best way is through separation. If you were to lay out the circuit board according to the schematic (input loop – converter IC – output loop) you’d be in good shape.
Q: You haven’t mentioned about CM and DM emissions. Are there cases where PCB radiation reduction for DM sometimes can cause increased CM and vice versa? Is there a universal PCB radiation reduction technique which can reduce both types of emissions simultaneously?
The very best way to reduce BOTH CM and DM EMI is through proper stack-up of your PCB. All signal traces should have an adjacent ground return plane and all power planes/traces should also have an adjacent ground return plane. We want to confine the digital signal electromagnetic waves between the copper trace and return plane from start to end. We want to confine any power network transients (also electromagnetic waves) between copper planes/traces and return plane as well. I did some recent experiments on DM and CM conducted emissions in my article on LISN Mate.
Q: You mentioned to keep DC-DC converters step away from processors and other digital circuits. However, low voltages rails (1V5, 0V8, etc.) need to be closer to the digital sinks, with penalty of voltage drops compromise voltage levels. For this case do you have any specific tip?
Figure 6 Sometimes it makes better sense to locate DC-DC converters near what they are powering. Just make sure to follow all the usual precautions, such as keeping current loops minimized and ensuring a solid return plane underneath.
Laying out PCBs while maintaining the goal of partitioning is always a tradeoff (Figure 6). Yes, sometimes (more often than not?) DC-DC converter circuits need to be located within the digital processing area. I would just caution you to maintain the general rules for DC-DC converter layout and ensure an adjacent solid return plane underneath all the digital and power conversion circuitry.
I’d also avoid locating power conversion too close to RF sections of the system. Some wireless module manufacturers suggest locating power conversion circuits near their modules and I’ve seen real problems with client designs that do this. There’s generally large E-fields generated around DC-DC converter inductors and switch nodes. Locating these fields near antennas is really bad news.
In addition, I’d highly recommend planning for the use of local shields over power conversion and digital processing sections. If not needed, then fine, but know that local shields are usually necessary (especially for physically small boards) and very hard to implement if there’s no attachment points planned in advance.
Q: Which is most effective, EMI filters (reflective LC filters) or EMI absorbers?
Ha! Well, my guess would be conventional filters would be better, because they can attenuate down to 40 dB, or so, however, their bandwidths would be potentially narrower than the more broadband ferrite absorber. Flexible ferrite absorber sheets (figures 7 and 8), on the other hand, are generally good for only 5 to 20 dB absorption. I suppose some experiments are called for. I’d refer you to my article on ferrite absorbers.
Figure 7 Measure ferrite absorber sheets using the microstrip attenuation method.
Figure 8 Here is an example absorption plot of the Arc-Tech WaveX ferrite absorber, which happens to work nicely in the normal cellular LTE and other wireless/GPS bands below 2 GHz.
Q: Which EMC book would you recommend?
I mentioned several above, but these favorites from my own library come immediately to mind (in no particular order):
This article was originally published on EDN.
—Kenneth Wyatt is president and principal consultant of Wyatt Technical Services.