PCB layout mitigates SET-related effects
Article By : STMicroelectronics
To lessen SET-related effects on voltage regulators, a PCB design layout must be with very low inductance and mutually coupling lines.
The RHFL4913A is an adjustable high-performance positive voltage regulator with exceptional radiation performance. It is tested in accordance with the Mil Std 883E method 1019.6 in ELDRS conditions.
As the RHFL4913A is manufactured with very high speed bipolar technology, the PCB layout must be designed with exceptional care, with very low inductance and low mutually coupling lines. Otherwise, high frequency parasitic signals may be picked up by the device resulting in system self-oscillation. The benefit is an SVR performance extended to far higher frequencies.
In the case of an FPGA power supply, as these devices are very sensitive to VDD transients beyond a small percentage of their nominal supply voltage (usually 1.5V), special attention must be taken to mitigate possible heavy-ion disturbances. The worst case heavy-ion effect can be summarised as the following: the RHFL4913A internal control loop being cut (opened) or short-circuited for a sub-microsecond duration. During such an event, the RHFL4913A die power element can either provide excessive current or current supply stoppage to the output for a duration of about 1ms, after which time the voltage regulator smoothly recovers to nominal operation.
To mitigate these “transients,” it is recommended to firstly implement the PCB layout using the following notes:
- Minimising series/parallel parasitic inductances of the PC path
- Using a low ESR 47μF tantalum filtering capacitor with a 470nF ceramic capacitor in parallel with the former (to reduce dynamic ESR)
With this implementation, the ELDO simulated worst transient case shows no more than a 90mV deviation from the nominal line voltage value.
Read more: Download the full application note
