PCI Express 3.0 needs reliable timing design

Article By : Amitava Banerjee & Jeetendra Ashok

Timing plays an essential role in determining the reliability of applications using PCI Express. With an understanding of the impact of the timing architecture on performance, developers can assure that systems will meet strict compliance requirements.

PCI Express (PCIe) is an important standard for chip-to-chip communications and serves as a standard for connecting motherboards to peripheral cards. It can be challenging, however, to implement the reference clock so that it meets the various requirements of the PCIe standard. Designers need to consider frequency, jitter, output standard, and other characteristics. With an understanding of the different PCIe architectures, their individual reference clock requirements, and how clock devices can help meet the various PCIe reference clock requirements, developers can design reliable systems.

PCIe architecture
To understand how the reference clock architecture is used in PCIe, look at the typical clock architecture in an example application like multifunction printers (MFP). The ASIC or SoC modules of MFPs have a built-in PCIe stack to simplify system design. A typical clocking interface of functional modules of an MFP is shown in Figure 1.

Multi-function printer clocking
Figure 1. A typical multifunction printer (MFP) module is driven by multiple clock sources.

Here, multiple modules need multiple clocks in multiple formats. They, do, however, need to be synchronized with respect to the central clock-generation device. Each module’s clock requirement is satisfied by separate clock generators. This approach of clock sourcing requires several different parts, with significant impact on PCB area, BOM complexity, power budget, and cost.

Designing with a clock generator provides a more integrated and more efficient approach for such complex system designs. In Figure 2, all individual clock sources shown in Figure 1 are replaced with a single clock generator IC.

MFP single clock generator IC
Figure 2. Individual clock sources in an MFP module can be replaced with a single clock generator IC.

PCIe clocking architectures
Figure 3 shows different types of industry-standard PCIe clocking architectures supported by high-performance clocks (Common Refclk, Separate Refclk, and Data Clocked Refclk).

PCIe clocking architectures
Figure 3. Clocks can support the different types of industry-standard PCIe clocking architectures.

The Common Reference clock (Common Refclk) architecture is the most commonly used architecture that uses spread-spectrum technology. Spread-spectrum clocking is used in applications to reduce electromagnetic interference (EMI). The clock source needs to be distributed to every PCIe device while keeping minimum skew between multiple clock outputs.

The Data Clocked Reference clock (Data Clocked Refclk) architecture is the simplest clock implementation because it requires only one clock source located at the transmitter. Here, receivers extract the embedded clock from the source clock.

In the Separate Reference clock architecture (Separate Refclk), a different clock source is used at each end of the communication link. Clock sources at both ends can still have a frequency accuracy of ±300 ppm because the PCIe standard allows for a total frequency deviation of 600 ppm between the transmitter and receiver.

The latest-generation PCIe specifications are listed in Table 1.

PCIe standard Year Released Nominal Bit Rate Data Throughput per channel Max Data Throughput (32 channels)
2.1 2007 5.0 Gbps 1 Gbps 32 Gbps
3.0 2010 8.0 Gbps 2 Gbps 62 Gbps
Table 1: The characteristics of PCIe link sources of clock jitter depends upon the PCIe standard in use.

The jitter performance of any clock IC may be affected if system design constraints are not properly followed. Typical noise sources of increased clock jitter are as follows:

  • If the on-board voltage regulator is a Buck/Boost type of circuit, the switching frequency and its higher order harmonics will get coupled with the internal Phase Lock Loop (PLL) and produce a noisy clock output.
  • The input-output buffers of interfaced ICs like DSPs, FPGAs, and SoCs may switch at a very high frequency. If the power supplies to the clock ICs are not properly isolated from the power supplies of the interfaced switching devices, noise may appear on the clock output.
  • A lack of proper shielding between two nearby clock lines can result mutual inductance between the two lines that causes crosstalk, which increases jitter.

Excessive clock jitter can make the clock device unsuitable for PCIe based applications because of its negative impact on system jitter margins and resulting increases the bit error rate (BER).

[Continue reading on EDN US: Spread-spectrum clock sources]

Amitava Banerjee is an Applications Engineer and Jeetendra Ashok is an Applications Manager, both at Cypress Semiconductor.

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